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A Study on Design of High-Speed Parallel Multiplier over GF(2m) using VCG

VCG를 사용한 GF(2m)상의 고속병렬 승산기 설계에 관한 연구

  • 성현경 (상지대학교 컴퓨터정보공학부)
  • Received : 2010.01.07
  • Accepted : 2010.01.13
  • Published : 2010.03.31

Abstract

In this paper, we present a new type high speed parallel multiplier for performing the multiplication of two polynomials using standard basis in the finite fields GF($2^m$). Prior to construct the multiplier circuits, we design the basic cell of vector code generator(VCG) to perform the parallel multiplication of a multiplicand polynomial with a irreducible polynomial and design the partial product result cell(PPC) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial with VCG circuits. The presented multiplier performs high speed parallel multiplication to connect PPC with VCG. The basic cell of VCG and PPC consists of one AND gate and one XOR gate respectively. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields GF($2^4$). Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper uses the VCGs and PPCS repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSL.

본 논문에서는 GF($2^m$)상의 표준기저를 사용한 새로운 형태의 VCG에 의한 고속병렬 승산회로를 제안하였다. 승산기의 구성에 앞서, 피승수 다항식과 기약다항식의 승산을 병렬로 수행하는 벡터 코드 생성기(VCG) 기본 셀을 설계하였고, VCG 회로와 승수 다항식의 한 계수와 비트-병렬로 승산하여 결과를 생성하는 부분 승산결과 셀(PPC)를 설계하였다. 제안한 승산기는 VCG와 PPC를 연결하여 고속의 병렬 승산을 수행한다. VCG 기본 셀과 PPC는 각각 1개의 AND 게이트와 1개의 XOR 게이트로 구성된다. 이러한 과정을 확장하여 m에 대한 일반화된 회로의 설계를 보였으며, 간단한 형태의 승산회로 구성의 예를 GF($2^4$)를 통해 보였다. 또한 제시한 승산기는 PSpice 시뮬레이션을 통하여 동작특성을 보였다. 본 논문에서 제안한 승산기는 VCG와 PPC을 반복적으로 연결하여 구성하므로, 차수 m이 매우 큰 유한체상의 두 다항식의 곱셈에서 확장이 용이하며, VLSI에 적합하다.

Keywords

References

  1. B. A. Laws and C. K. Rushforth, "A Cellular Array Multiplier for GF($2^{m}$') ," IEEE Trans. Computers, vol. C-20, pp. 1573-1578, Dec. 1971. https://doi.org/10.1109/T-C.1971.223173
  2. H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yaeh and I. S. Reed, "A VLSI Design of a Pipelining Reed-Solomon Decoder," IEEE Trans. Computers, vol. C-34, pp. 393-403, May 1985. https://doi.org/10.1109/TC.1985.1676579
  3. C. C. Wang, T. K. Truong, H. M. Shao, L. J. Deutsch, J. K. Omura and I. S. Reed, "VLSI Architecture for Computing Multiplications and Inverses in GF($2^{m}$) ," IEEE Trans. Computers, vol. C-34, pp. 709-717, Aug. 1985. https://doi.org/10.1109/TC.1985.1676616
  4. S. B. Wicker and V. K. Bhargava, Reed- Solomon Codes and Their Applications, IEEE Press, 1994.
  5. 3rd Generation Partnership Project., "Technical specification group GSM/EDGE radio access network; channel coding (release 5)," Tech. Rep. 3GPP TS 45.003 V5.6.0, June 2003.
  6. C. K. Koc and B. Sunar, "Low Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields," IEEE Trans. Computers, vol. 47, no. 3, pp. 353-356, Mar. 1998. https://doi.org/10.1109/12.660172
  7. C. S. Yeh, I. S. Reed and T. K. Truong, "Systolic Multipliers for Finite Field GF($2^{m}$)," IEEE Trans. Computers, vol. C-33, pp. 357-360, Apr. 1984. https://doi.org/10.1109/TC.1984.1676441
  8. Y. Wang, Z. Tian, X. Bi and Z. Niu, "Efficient Multiplier over Finite Field Represented in Type II Optimal Normal Basis," Proceedings of the Sixth International Conference on Intelligent Systems Design and Applications (ISDA '06), 2006.
  9. N. Petra, D. de Caro and A. G.M. Strollo, "A Novel Architecture for Galois Fields GF($2^{m}$) Multipliers Based on Mastrovito Scheme," IEEE Trans. Computers, vol. 58, no. 11, pp.1470-1483, Nov. 2007.
  10. H. Wu and H. A. Hasan and L. F. Blake, "New Low-Complexity Bit-Parallel Finite Fields Multipliers Using Weekly Dual Basis," IEEE Trans. Computers, vol. 47, no. 11, pp. 1223-1234, Nov. 1998. https://doi.org/10.1109/12.736433
  11. A. Halbutogullari and C. K. Koc, "Mastrovito Multiplier for General Irreducible Polynomials," IEEE Trans. Computers, vol. 49, no. 5, pp. 503-518, May 2000. https://doi.org/10.1109/12.859542
  12. E. D. Mastrovito, "VLSI Design for Multiplication on Finite Field GF($2^{m}$)," Proc. International Conference on Applied Algebraic Algorithms and Error-Correcting Code, AAECC-6, Roma, pp. 297-309, July 1998.
  13. R. Lidl, H. Niederreiter and P. M. Cohn, Finite Fields, Addison-Wesley, Reading, Massachusetts, 1983.
  14. S. B. Wicker and V. K. Bhargava, Error Correcting Coding Theory, McGraw-Hill, New York, 1989.
  15. A. R. Masoleh and M. A. Hasan, "A New Construction of Massey-Omura Parallel Multiplier over GF($2^{m}$)," IEEE Trans. Computers, vol. 51, no. 5, pp. 511-520, May 2002. https://doi.org/10.1109/TC.2002.1004590
  16. S. Kumar, T. Wollinger and C. Paar, "Optimum Digit Serial GF($2^{m}$) Multipliers for Curve-Based Cryptography," IEEE Trans. Computers, vol. 55, no. 10, pp.1306-1311, Oct. 2006. https://doi.org/10.1109/TC.2006.165
  17. A. H. Narnin, H. Wu and M. Ahma야, "Comb Architectures for Finite Field Multiplication in $IF_{2m}$," IEEE Trans. Computers, vol. 56, no. 7, pp.909-916, July 2007. https://doi.org/10.1109/TC.2007.1047
  18. K. Sakiyarna, L. Batina, B. Preneel and I. Verbauwhede, "Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over $GF(2^{m)}$," IEEE Trans. Computers, vol. 56, no. 9, pp.1269-1282, Sep. 2007. https://doi.org/10.1109/TC.2007.1071