Journal of information and communication convergence engineering

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Analysis on DIBL of DGMOSFET for Device Parameters

  • Jung, Hak-Kee (Department of Electronic Engineering, Kunsan National University)
  • Received : 2011.09.15
  • Accepted : 2011.11.01
  • Published : 2011.12.31
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Abstract

This paper has studied drain induced barrier lowering(DIBL) for Double Gate MOSFET(DGMOSFET) using analytical potential model. Two dimensional analytical potential model has been presented for symmetrical DGMOSFETs with process parameters. DIBL is very important short channel effects(SCEs) for nano structures since drain voltage has influenced on source potential distribution due to reduction of channel length. DIBL has to be small with decrease of channel length, but it increases with decrease of channel length due to SCEs. This potential model is used to obtain the change of DIBL for DGMOSFET correlated to channel doping profiles. Also device parameters including channel length, channel thickness, gate oxide thickness and doping intensity have been used to analyze DIBL.

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References

  1. Technology Roadmap on Semiconductors, 2007 edition, Semiconductor Industry Association. URL: http://public.itrs.net.
  2. A.Kranti, T.M.Chung, D.Flandre and J.P.Raskin, "Analysis of quasi double gate method for performance prediction of deep submicron double gate SOI MOSFETs," Semicond. Sci. Technol., vol.20, pp.423-429, 2005. https://doi.org/10.1088/0268-1242/20/5/017
  3. F.Djeffal, M.A.Abdi, Z.Dibi, M.Chahdi and A.Benhaya, "A neutral approach to study the scaling capability of the undoped Double- Gate and cylindrical Gate All Arround MOSFETs," Materials Sci. and Eng:B, vol.147, pp.239-244, 2008. https://doi.org/10.1016/j.mseb.2007.08.034
  4. A.Anwar and I.Hossain,"A Comparative Numerical Simulation of a Nanoscaled Body on Insulator FinFET," Proc. 27th International Conference on Microelectronics(MIEL2010), pp.413-416, 2010.
  5. G.Zhang, Z.Shao and K.Zhou,"Threshold voltage model for short channel FD-SOI MOSFETs with vertical Gaussian profile," IEEE Trans. Electron Devices, vol.55, pp.803-809, 2008. https://doi.org/10.1109/TED.2007.914832
  6. P.K.Tiwari,S.Kumar, S.Mittal, V.Srivastava, U.PandeyK and S.Jit,"A 2D Analytical Model of the Channel Potential and Threshold Voltage of Double-Gate(DG) MOSFETs With Vertical Gaussian Doping Profile," IMPACT-2009,pp.52-55,2009.
  7. H.K.Jung, J.H.Han, J.I.Lee and S.Dimitrijev,"Analysis of DIBL for DGMOSFET Using Structure and Process Parameters," Proc. of ICKIMICS2011, vol.4, no.1, pp.289-292,2011.
  8. Q.Chen, B.Agrawal and J.D.Meindl,"A Comprehensive Analytical Subthreshold Swing(S) Model for Double-Gate MOSFETs," IEEE Trans. Electron Devices, vol.49, pp.1086-1090, 2002. https://doi.org/10.1109/TED.2002.1003757