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A Design of 8-bit Switched-Capacitor Cyclic DAC with Mismatch Compensation of Capacitors

캐패시터 부정합 보정 기능을 가진 8비트 스위치-캐패시터 사이클릭 D/A 변환기 설계

  • 양상혁 (고려대 공대 전기전자공학과) ;
  • 송지섭 (고려대 공대 나노반도체공학과) ;
  • 김석기 (고려대 공대 전기전자전파공학과) ;
  • 이계신 ;
  • 이용민 (선문대 정보디스플레이학과)
  • Received : 2010.12.16
  • Accepted : 2011.01.24
  • Published : 2011.02.01

Abstract

A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.

Keywords

References

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