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The Korean Institute of Electrical Engineers (대한전기학회)
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A 10bit 1MS/s 0.5mW SAR ADC with Double Sampling Technique

더블 샘플링 기법을 사용한 10bit 1MS/s 0.5mW 축차 비교형 아날로그-디지털 변환기

  • 이호규 (고려대학교 공과대학 전자전기공학과) ;
  • 김무영 (고려대학교 공과대학 전자전기공학과) ;
  • 김철우 (고려대학교 공과대학 전자전기공학과)
  • Received : 2010.12.16
  • Accepted : 2011.01.24
  • Published : 2011.02.01
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Abstract

This paper introduces the 10b 1MS/s SAR ADC with double sampling technique to reduce the power consumption. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.11um2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB at 484kHz input frequency, respectively. The implemented data converter consumes 507uW with 1.2-V supply.

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References

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