Journal of Electrical Engineering and Technology

The Korean Institute of Electrical Engineers (대한전기학회)
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Selective Growth of Carbon Nanotubes using Two-step Etch Scheme for Semiconductor Via Interconnects

  • Lee, Sun-Woo (Dept. of Electrical Information, Inha Technical Colleg) ;
  • Na, Sang-Yeob (Dept. of Computer Science, Namseoul University)
  • Received : 2010.07.16
  • Accepted : 2010.11.10
  • Published : 2011.03.01
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Abstract

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

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