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The Korean Institute of Electrical Engineers (대한전기학회)
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A Test Vector Reordering for Switching Activity Reduction During Test Operation Considering Fanout

테스트시 스위칭 감소를 위해 팬 아웃을 고려한 테스트벡터 재 정렬

  • 이재훈 (여주대학 게임기획비즈니스과) ;
  • 백철기 (성균관대학교 정보통신공학부) ;
  • 김인수 (장안대학교 IT학부 인터넷정보통신과) ;
  • 민형복 (성균관대학교 정보통신공학부)
  • Received : 2011.01.24
  • Accepted : 2011.04.07
  • Published : 2011.05.01
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Abstract

Test vector reordering is a very effective way to reduce power consumption during test application. But, it is time-consuming and complicated processes, and it does not consider internal circuit structure, which may limit the effectiveness. In this paper, we order test vectors using fanout count of primary inputs that consider the internal circuit structure, which may reduce the switching activity. Then, we reorder test test vectors again by using Hamming distance between test vectors. We proposed FOVO algorithm to perform these two ideas. FOVO is an effective way to reduce power consumption during test application. The algorithm is applied to benchmark circuits and we get an average of 3.5% or more reduction of the power consumption.

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References

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