Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Construction of High-Speed Parallel Multiplier on Finite Fields GF(3m)

유한체 GF(3m)상의 고속 병렬 승산기의 구성

  • 최용석 (상지대학교 컴퓨터정보공학부) ;
  • 박승용 (재능대학 컴퓨터정보과) ;
  • 성현경 (상지대학교 컴퓨터정보공학부)
  • Received : 2010.10.25
  • Accepted : 2011.02.17
  • Published : 2011.03.31
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Abstract

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and compose the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells that have a mod(3) addition gate and a mod(3) multiplication gate. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

본 논문에서는 유한체 $GF(3^m)$상에서 모든 항에 0이 아닌 계수가 존재하는 기약 다항식에 대하여 m이 홀수 및 짝수인 경우인$GF(3^m)$상의 승산 알고리즘을 제시하였으며, 제시된 승산 알고리즘을 이용하여 고속의 병렬 입-출력 모듈구조의 승산기를 구성하였다. 제시한 승산기의 구성은 $(m+1)^2$개의 동일한 기본 셀들로 설계되었으며, 기본 셀은 1개의 mod(3) 가산 게이트와 1개의 mod(3) 승산 게이트로 구성하였다. 셀에 래치를 사용하지 않았으므로 회로가 가장 간단하며, 셀당 지연시간도 $T_A+T_X$로서 가장 적다. 본 연구에서 제안한 승산기는 규칙성과 셀 배열에 의한 모듈성을 가지므로 m이 큰 회로의 확장이 용이하며 VLSI회로 실현에 적합할 것이다.

Keywords

References

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