IEMEK Journal of Embedded Systems and Applications (대한임베디드공학회논문지)

Institute of Embedded Engineering of Korea (대한임베디드공학회)
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The Efficient Buffer Size in A Dual Flash Memory Structure with Buffer System

이중 NAND 플래시 구조의 버퍼시스템에서 효율적 버퍼 크기

  • 정보성 (경상대학교 ERI 제어계측공학과) ;
  • 이정훈 (경상대학교 ERI 제어계측공학과)
  • Received : 2011.07.04
  • Accepted : 2011.08.16
  • Published : 2011.12.31
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Abstract

As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.

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References

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