IEMEK Journal of Embedded Systems and Applications (대한임베디드공학회논문지)

Institute of Embedded Engineering of Korea (대한임베디드공학회)
권호 표지
DOI QR코드

DOI QR Code

Performane Modeling of Flash Memory Storage Systems Using Simulink

시뮬링크를 이용한 플래시메모리 저장장치 성능 모델링

  • 민항준 (서울대학교 전기컴퓨터공학부) ;
  • 박정수 (서울대학교 전기컴퓨터공학부) ;
  • 이주일 (서울대학교 전기컴퓨터공학부) ;
  • 민상렬 (서울대학교 전기컴퓨터공학부) ;
  • 김강희 (숭실대학교 정보통신전자공학부)
  • Received : 2011.02.28
  • Accepted : 2011.04.11
  • Published : 2011.10.31
Download PDF
⟨ Previous Next ⟩

Abstract

The complexity of flash memory based storage systems is high due to diverse host interfaces and other design choices such as mapping granularity, flash memory controller execution models and so on. Thus, it is possible that the actual performance after implementation is not consistent with the target performance. This paper demonstrates that the performance prediction of flash memory based storage systems is possible through performance modeling that takes into account various design parameters. In the performance modeling, the FTL, which is the core element of flash memory based storage systems, is modeled as a set of (copy-on-write) logs and their interactions. Also, the flash memory controller is modeled based on the classification proposed in the design of the Ozone flash controller. In this study, the performance model has been implemented using Simulink and experimental results are presented and analyzed.

Keywords

References

  1. S. W. Lee, D. J. Park, T. S. Chung, D. H. Lee, S. Park, and H. J. Song, "A log buffer-based flash translation layer using fully-associative sector translation", ACM Transactions on Embedded Computing Systems, Vol.6, No.18, 2007.
  2. J. U. Kang, H. Jo, J. S. Kim, and J. Lee, "A superblock-based flash translation layer for NAND flash memory", In Proceedings of the 6th ACM & IEEE International conference on Embedded Software (EMSOFT '06), pp. 161-170, 2006.
  3. J. S. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho, "A space-efficient flash translation layer for compactflash systems", IEEE Transactions on Consumer Electronics, Vol.48, Issue 2, pp. 366-375, 2002. https://doi.org/10.1109/TCE.2002.1010143
  4. N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. Manasse, and R. Panigrahy, "Design tradeoffs for SSD performance", In Proceedings of USENIX Annual Technical Conference, pp. 57-70, 2008.
  5. J. S. Bucy, J. Schindler, S. W. Schlosser, and G. R. Ganger, "The DiskSim simulation environment version 4.0 reference manual", Technical report, CMU-PDL-08-101, Carnegie Mellon University, 2008.
  6. Y. Kim, B. TauraS. A. Gupta, and B. Urgaonkar, "FlashSim: A Simulator for NAND flash-based solid-state drives", Technical report, CSE 09-008, Penn State University, 2009.
  7. E. H. Nam, B. S. J. Kim, H. Eom, and S. L. Min, "Ozone (O3): An out-of-order flash memory controller architecture", IEEE Transactions on Computers. Vol. 60, No. 5, pp. 653-666, 2011. https://doi.org/10.1109/TC.2010.209
  8. M, Rosenblum, and J. K. Ousterhout, "The design and implementation of a log-structured file system", In Proceedings of th thirteenth ACM Symposium on Operating Systems Principles (SOSP '91), pp. 1-15, 1991.
  9. H. Cho, D. Shin, and Y. Eom, "KAST:K-associative sector translation for NAND flash memory in real-time systems", IEEE DATE Conference, 2009.
  10. S. Y. Park, W. Cheon, Y. Lee, M. S. Jung, W. Cho, and H. Yoon, "A re-configurable FTL architecture for NAND flash-based applications", In Proceedings of International Workshop on Rapid System Prototyping, 2007.
  11. 민항준, 박정수, 이주일, 민상렬, "시뮬링크를 이용한 플래시메모리 제어기의 성능 모델링", 2010 대한임베디드공학회 추계학술대회 논문집, 2010.
  12. E. Gal, S. Toledo, "Algorithms and data structures for flash memories", ACM Computing Surveys, Vol.37, No.2, pp. 138-163, Jun. 2005. https://doi.org/10.1145/1089733.1089735