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A performance analysis of layered LDPC decoder for mobile WiMAX system

모바일 WiMAX용 layered LDPC 복호기의 성능분석

  • Received : 2010.12.07
  • Accepted : 2010.12.27
  • Published : 2011.04.30

Abstract

This paper describes an analysis of the decoding performance and decoding convergence speed of layered LDPC(low-density parity-check) decoder for mobile WiMAX system, and the optimal design conditions for hardware implementation are searched. A fixed-point model of LDPC decoder, which is based on the min-sum algorithm and layered decoding scheme, is implemented and simulated using Matlab model. Through fixed-point simulations for the block lengths of 576, 1440, 2304 bits and the code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 specified in the IEEE 802.16e standard, the effect of internal bit-width, block length and code rate on the decoding performance are analyzed. Simulation results show that fixed-point bit-width larger than 8 bits with integer part of 5 bits should be used for acceptable decoding performance.

본 논문에서는 모바일 WiMAX용 layered LDPC(low-density parity-check) 복호기의 복호성능 및 복호 수렴속도 분석을 통해 LDPC 복호기의 하드웨어 구현을 위한 최적의 설계조건을 탐색하였다. 최소합 알고리듬과 layered 복호방식을 적용한 LDPC 복호기의 고정소수점 Matlab 모델을 개발하고 시뮬레이션 하였다. IEEE 802.16e 표준에 제시된 블록길이 576, 1440, 2304 비트와 부호율 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6에 대해 고정소수점 비트 폭, 블록길이, 부호율 등이 복호성능에 미치는 영향을 분석하였으며, 고정소수점 비트 폭이 8 비트 이상이고 정수부분이 5 비트 이상일 때 안정된 복호성능이 얻어짐을 확인하였다.

Keywords

References

  1. R.G. Gallager, Low-Density Parity-Check Codes, IRE Trans. Inform. Theory, pp. 21- 28, vol. 8, no. 1, Jan. 1962. https://doi.org/10.1109/TIT.1962.1057683
  2. D.J.C. MacKay and R. M. Neal, "Near Shannon limit performance of low density parity check codes," IEE Electronic Letter, vol. 32, no. 18, pp. 1645-1646, Aug. 1996. https://doi.org/10.1049/el:19961141
  3. IEEE 802.11n: Wireless LAN medium access control(MAC) and physical layer (PHY) specifications: enhancements for higher throughput, IEEE Std. P802.11n/D7.0, 2008.
  4. IEEE 802.16e, Part 16: Air interface for fixed and mobile broadband wireless access systems, IEEE std 802.16e-2005, Feb. 2006.
  5. DVB-S2 Draft ETSI EN 302 307 V1.1.1 (2004-06), ETSI
  6. T.J. Richardson and R.L. Urbanke, "The capacity of low-density parity-check code under message-passing decoding," IEEE Trans. Inform. Theory, vol. 47, pp. 599-618, Feb. 2001. https://doi.org/10.1109/18.910577
  7. A.J. Blanksby and C.J. Howland, "A 690- mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check codes decoder," IEEE J. of Solid-State Circuits, vol. 37, no. 3, pp. 404-412, Mar. 2002. https://doi.org/10.1109/4.987093
  8. M.M. Mansour and N.R. Shanbhag, "A 640- Mb/s 2048-bit programmable LDPC decoder chip," IEEE J. of Solid-State Circuits, vol. 41, no. 3, pp. 684-698, Mar. 2006. https://doi.org/10.1109/JSSC.2005.864133
  9. X.Y. Shih, C.Z. Zhan, C.H. Lin, and A.Y. Wu, "An 8.29mm 52mW multi-mode LDPC decoder design for mobile WiMAX system in 0.13um CMOS process," IEEE J. of Solid-State Circuits, vol. 43, no. 3, pp. 672-683, Mar. 2008. https://doi.org/10.1109/JSSC.2008.916606
  10. J. Cho, N.R. Shanbhag, W. Sung, "Low- power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard," IEEE workshop on Signal Processing Systems(SiPS 2009), pp. 40-45, 2009.
  11. M. Karkooti, P. Radosavljevic and J.R. Cavallaro, "Configurable, high throughput, irregular LDPC decoder architecture: trade- off analysis and implementation," Proc. of Application-Specific Systems, Architectures and Processors(ASAP), pp. 360-367, 2006.
  12. G. Masera, F. Quaglio, and F. Vacca, "Implementation of flexible LDPC decoder," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 6, pp. 542-546, Jun. 2007. https://doi.org/10.1109/TCSII.2007.894409
  13. D. Bao, B. Xiang, R. Shen, A. Pan, Y. Chen, and X. Zeng, "Programmable Archi- tecture for Flexi-Mode QC-LDPC Decoder Supporting Wireless LAN/MAN Application and Beyond," IEEE Trans. on Circuits and Systems-I, vol. 57, no. 1, pp. 125-138, Jan. 2010. https://doi.org/10.1109/TCSI.2009.2019395
  14. R.M. Tanner, "A recursive approach to low complexity codes," IEEE Trans. on Inform. Theory, vol. 27, no. 5, pp. 533-547, Sep. 1981. https://doi.org/10.1109/TIT.1981.1056404
  15. M. Fossorier, M. Mihaljevic and H. Imai, "Reduced complexity iterative decoding of low-density parity check codes based on belief propagation," IEEE Trans. Commun., vol. 47, pp. 673-680, May. 1999. https://doi.org/10.1109/26.768759
  16. F. Zarkeshvari and A. Banihashemi, "On implementation of min-sum algorithm for decoding low-density parity-check (LDPC) codes", Proc. of IEEE GLOBECOM, vol. 2, pp. 1349-1353, Nov. 2002.
  17. M.M. Mansour and N.R. Shanbhag, "High- throughput LDPC decoders," IEEE Trans. Very Large Scale Integration(VLSI) Syst., vol. 11, no. 6, pp. 976-996, Dec. 2003. https://doi.org/10.1109/TVLSI.2003.817545
  18. T. Zhaizg, Z. Wang and K.K. Parhi, "On finite precision implementation of low density parity check codes decoder," Proc. of IEEE International Symp. on Circuits and Systems(ISCAS), vol. 4, pp. 202-205, 2001.
  19. 박해원, 나영헌, 신경욱, "IEEE 802.11n WLAN용 다중모드 LPDC 복호기의 최적 설계조건 분석", 한국해양정보통신학회 논문지, 제15권 2호, pp. 432-438, 2011. 2.