Journal of the Korea Society of Computer and Information (한국컴퓨터정보학회논문지)

Korean Society of Computer Information (한국컴퓨터정보학회)
권호 표지
DOI QR코드

DOI QR Code

Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache

코어와 L2 캐쉬의 수직적 배치 관계에 따른 3차원 멀티코어 프로세서의 온도 분석

  • Son, Dong-Oh (School of Electronics and Computer Engineering, Chonnam National University) ;
  • Ahn, Jin-Woo (School of Electronics and Computer Engineering, Chonnam National University) ;
  • Park, Jae-Hyung (School of Computer Engineering and Information Technology, University of Ulsan) ;
  • Kim, Jong-Myon (School of Computer Engineering and Information Technology, University of Ulsan) ;
  • Kim, Cheol-Hong (School of Computer Engineering and Information Technology, University of Ulsan)
  • 손동오 (전남대학교 전자컴퓨터공학부) ;
  • 안진우 (전남대학교 전자컴퓨터공학부) ;
  • 박재형 (울산대학교 컴퓨터정보통신공학부) ;
  • 김종면 (울산대학교 컴퓨터정보통신공학부) ;
  • 김철홍 (울산대학교 컴퓨터정보통신공학부)
  • Received : 2010.11.19
  • Accepted : 2011.03.10
  • Published : 2011.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.

멀티코어 프로세서를 설계하는데 있어서 구성요소들을 연결하는 와이어 길이의 증가로 인한 지연 현상은 성능향상에 큰 걸림돌이 되고 있다. 멀티코어 프로세서의 와이어 지연 문제를 해결하기 위하여 최근에는 3차원 구조의 멀티코어 프로세서 설계 기술이 많은 주목을 받고 있다. 3차원 구조 멀티코어 프로세서 설계 기술은 코어들을 수직으로 적층함으로써, 물리적인 연결망 길이를 크게 감소시켜 성능향상과 함께 연결망에서 소비되는 전력을 줄일 수 있다. 하지만 많은 전력을 소모하는 회로를 수직으로 적층함으로써 전력밀도가 증가하여 프로세서 내부의 온도가 크게 상승하는 문제를 가지고 있다. 본 논문에서는 3차원 구조 멀티코어 프로세서에서의 발열문제를 해결 할 수 있는 플로어플랜 방법을 제안하기 위해 칩 내부에 적층되는 코어의 수직적 배치 형태를 다양하게 변화시키면서 그에 따른 온도 변화를 살펴보고자 한다. 실험 결과를 통해, 프로세서 내부의 온도 감소를 위해서는 코어와 L2 캐쉬를 수직으로 인접하게 적층함으로써 코어의 온도를 낮추는 기법이 매우 효과적임을 알 수 있다. 코어와 코어가 수직으로 상호 인접하는 플로어플랜과 비교하여, 코어와 L2 캐쉬를 수직으로 인접하게 배치시키는 기법이 4-레이어 구조의 경우에는 평균 22%, 2-레이어 구조의 경우 평균 13%의 온도 감소 효과를 보임을 알 수 있다.

Keywords

References

  1. P. Kongetira, K. Aingaran, K. Olukotun, "Niagara: A 32-way multithreaded SPARC processor," IEEE Micro, vol. 25, no. 2, pp.21-29, March-April. 2005. https://doi.org/10.1109/MM.2005.35
  2. C. Zhu, Z. Gu, L. Shang, R. P. Dick, R. Joseph, " Three-dimensional chip-multiprocessor run-time thermal management," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1479-1492, Sonoma, CA, USA, Aug, 2008. https://doi.org/10.1109/TCAD.2008.925793
  3. S. W. Yoon, D. W. Yang, J. H. Koo, M. Padmanathan, and F. Carson, "3D TSV processes and its assembly/Packaging technology," In Proceedings of IEEE International Conference on 3D System Integration, pp.1-5, SanFrancisco, USA, Sep. 2009.
  4. E. Wong, Sung Kyu Lim, "3D Floorplanning with Thermal Vias," In Proceedings of the conference on Design, Automation and Test in Europe, pp.878-883, Munich, Germany, Mar. 2006.
  5. A. K. Coskun, J. L. Ayala, D. Atienza, T. S. Rosing, and Y. Leblebici, "Dynamic Thermal Management in 3D Multicore Architectures," In Proceedings of Design, Automation & Test in Europe Conference & Exhibition, pp.1410-1415, Nice, France, Apr. 2009.
  6. J. W. Joyner, Zarkesh-Ha. P, Meindl J.D, "A Stochastic Global Net-length Distribution for a Three-Dimensional System on Chip (3D-SoC)," In Proceedings of the 14th IEEE International ASIC/SOC Conference, pp.147-151, Arlington, VA, USA, Sep. 2001.
  7. K. Puttaswamy, G. H. Loh, "Thermal Analysis of a 3D Die Stacked High Performance Microprocessor," In Proceedings of ACM Great Lakes Symposium on VLSI, pp. 19-24, Philadelphia, USA, 2006.
  8. Coskun A.K, Kahng A.B, Rosing T.S, "Temperatureand Cost-Aware Design of 3D Multiprocessor Architectures," In Proceedings of 12th Euromicro conference on Digital System Design, Architectures, Methods and Tools, pp.183-190, Patras, Greece, Aug. 2009.
  9. Hung W.-L, Link G.M, Yuan Xie, Vijaykrishnan N., Irwin M.J, "Interconnect and Thermal-aware Floorplanning for 3D Microprocessors," In Proceeding of the 7th ISQED, pp.98-104, San Jose, CA, USA, March. 2006.
  10. P. N. Guo, C. K. Cheng, and T. Yoshimura, "An 0-Tree representation of non-slicing floorplan and its applications," In Proceeding of Design Automation Conference(DAC), pp.268-273, New Orleans, USA, lune. 1999.
  11. C. H. Tsai, S. M. Kang, "Cell-Level Placement for Improving Substrate Thermal Distribution," IEEE Tram. On Computer.-Aided Des, vol. 19, no. 2, pp. 253-266, Feb. 2000. https://doi.org/10.1109/43.828554
  12. K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. S. Nakatake, H. Murata, K. Fujiyoshi, Y. Kajitani, "Module placement on BSG-structure and IC layout applications," In Proceedings of IEEE/ACM ICCAD, pp.484-491, San Jose, USA, Nov. 1996.
  13. H. Murata, E. S. Kuh, "Sequence Pair Based Placement Method for Hard/Soft/Pre-placed Modules," In Proceeding of International Symposium on Physical Design(ISPD), pp.167-172, Monterey, California, ,USA , April. 1998.
  14. Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu, "B*-Trees: A New Representation for Non-Slicing Floorplans," In Proceeding of DAC, pp. 458-463, Los Angeles, California, USA, June, 2000.
  15. W. Chu, W. Kao, "A Three-Dimensional Transient Electrothermal Simulation System for ICs," In Proceeding of THERMINIC Workshop, pp. 201- 207, Villard de Lans, France, Sept, 1995.
  16. J. Cong, J. Wei, Y. Zhang, "A Thermal-Driven Floorplanning Algorithm for 3D ICs," In Proceeding of ICCAD, pp. 306-313, Dusit Resort, Pattaya Beach, Thailand, Nov, 2004
  17. T. Chiang, S. Souri, C. Chui, K. Saraswat, "Thermal Analysis of Heterogenous 3D ICs with Various Integration Scenarios," In Proceeding of International Electron Devices Meeting(IEDM) Technical Digest, pp. 31.2.1-31.2.4, Washington, DC , USA, Dec, 2001.
  18. K. Banerjee, et al., "3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration," In Proceedings of the IEEE, vol. 89, no. 5, pp. 602-633, May 2001. https://doi.org/10.1109/5.929647
  19. D. C. Burger, and T. M. Austin, "The SimpleScalar tool set, version 2.0," ACM SIGARCH CAN, vol. 25, no. 3, pp. 13-25, Jun. 1997. https://doi.org/10.1145/268806.268810
  20. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: a framework for architectural-level power analysis and optimizations," in Proceedings of the 27th International Symposium on Computer Architecture, pp.83-94, Jun. 2000.
  21. R. E. Kessler, E. J. McLellan, and D. A. Webb, "The Alpha 21264 Microprocessor Architecture," In Proceedings of the ICCD '98, pp.90-95, Austin, USA, Aug. 2002.
  22. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranaratanan, and D. Tarjan, "Temperature-Aware Microarchitecture," In Proceedings of the 30th annual international symposium on Computer architecture, pp.83-94, Apr. 2002.
  23. SPEC CPU2000 Benchmarks, available at http://www.specbench.org
  24. Microarchitectural Floorplanning for Thermal Management: A Technical Report, available at http://www.cs.virginia.edu/-techrep/CS-2005 -08.pdf

Cited by

  1. 코어 내부 구성요소와 L2 캐쉬의 배치 관계에 따른 멀티코어 프로세서의 온도 분석 vol.19, pp.4, 2011, https://doi.org/10.9708/jksci.2014.19.4.001