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Low Power Detection Circuit for a Capacitive Fingerprint Sensor

용량성 지문센서를 위한 저전력 감지회로

  • 정승민 (한신대학교 IT대학 디지털융합학부)
  • Received : 2011.05.27
  • Accepted : 2011.05.27
  • Published : 2011.06.30

Abstract

A modified capacitive detection circuit of charge sharing scheme is proposed, which reduces the static power dissipation and increases the voltage difference between a ridge and valley more than a conventional circuit. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process, 40MHz condition. The result shows about 47% power dissipation reduction and 90% improvement of difference between a ridge and valley sensing voltage. The proposed circuit is layout without area increasing of a one pixel.

본 논문에서는 개선된 회로를 적용한 용량성 센서용 저전력 전하분할 방식의 지문센서 감지회로를 제안하고 있다. 제안된 회로는 기존회로에 비하여 전력소모를 크게 줄이고 융선과 골간의 감지전압차를 확대하였다. 설계된 회로는 40MHz 동작주파수, 3.3V 전원에 $0.35{\mu}m$ 표준 CMOS 공정 파라미터를 적용하여 시뮬레이션을 실시하였다. 검증결과 47% 전력소모 감소를 보였고 융선과 골간의 감지 전압 차에 있어서 90% 증가를 나타내었다. 제안된 회로는 면적의 증가 없이 기존 픽셀 레이아웃에 구현되었다.

Keywords

References

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