DOI QR코드

DOI QR Code

RMS Current Estimation Technique for Reliability Analysis of Multiple Semiconductor Interconnects

신뢰성 해석을 위한 반도체 다중연결선의 RMS 전류 추정 기법

  • Received : 2011.01.19
  • Accepted : 2011.06.27
  • Published : 2011.08.01

Abstract

As process parameters scale, interconnect width are reduced rapidly while the current flowing through interconnects does not decrease in a proportional manner. This effect increases current density in metal interconnects which may result in poor reliability. Since RMS(root-mean-square) current limits are used to evaluate self-heating and short-time stress failures caused by high-current pluses, RMS current estimation is very important to guarantee the reliability of semiconductor systems. Hence, it is critical to estimate the current limits through interconnects earlier in semiconductor design stages. The purpose of this paper is to propose a fast, yet accurate RMS current estimation technique that can offer a relatively precise estimate by using closed-form equations. The efficiency and accuracy of the proposed method have been verified through simulations using HSPICE for a vast range of interconnect parameters.

Keywords

References

  1. Failure Mechanisms and Models for Semiconductor Devices, in JEDEC publication JEP122C, 2006.
  2. I. A. Belch and J. Sello, "The Failure of Thin Aluminum Current-Carrying Strips on Oxidized Silicon," Physics of Failure in Electronics, vol. 5, pp. 496-505, 1966.
  3. James R. Black, "Electromigration - A Brief Survey and Some Recent Results," IEEE Trans. on Electron Devices, vol. ED-16(no. 4), pp. 338, 1969.
  4. K. Banerjee and A. Mehrotra, "Global Interconnect Warming," IEEE Circuits and Devices Magazine, pp. 16-32, 2001.
  5. A. R. Oriani, "Thermomigration in Solid Metals," Journal of Physics and Chemistry of Solids, pp. 339-351, 1969.
  6. N. S. Nagaraj, F. Cano, H. Haznedar and D. Young, "A Practical Approach to Static Signal Electromigration Analysis," in Proc. ACM/IEEE Design Automation Conference, pp. 572-577, 1998.
  7. D. Blaauw, C. Oh, V. Zolotov and A. Dasgupta, "Static Electromigration Analysis for On-Chip Signal Electromigration Analysis," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, pp. 39-48, 2003. https://doi.org/10.1109/TCAD.2002.805728
  8. J. E. Hall, D. E. Hocevar, P. Yang and M. J. McGraw, "SPIDER - A CAD System for Modeling VLSI Metallization Patterns," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, pp. 1023-1031, 1978.
  9. R. H. Tu et al., "Berkeley Reliability Tools - BERT," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 1524-1534, 1993. https://doi.org/10.1109/43.256927
  10. D. F. Frost and K. F. Poole, "RELIANT: A Reliability Analysis Tool for VLSI Interconnects," IEEE Journal of Solid-State Circuits, vol. 24, pp. 458-462, 1989. https://doi.org/10.1109/4.18608
  11. C. Teng, Y. Cheng, E. Rosenbaum and S. Kang, "iTEM: A Temperature-Dependent Electromigration Reliability Diagnosis Tool," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, pp. 882-893, 1997. https://doi.org/10.1109/43.644613
  12. K. Agarwal and F. Liu, "Efficient Computation of Current Flow in Signal Wires for Reliability Analysis," in Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 741-746, 2007.
  13. M. Celik, L. Pileggi and A. Odabasioglu, IC Interconnect Analysis, Kluwer Academic Publishers, 2002.
  14. L. T. Pillage and R. A. Rohrer, "Asymptotic Waveform Evaluation for Timing Analysis," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, pp. 352-366, 1990. https://doi.org/10.1109/43.45867
  15. L. T. Pillage, R. A. Rohrer and C. Visweswariah, Electronic Circuit and System Simulation Methods, McGraw-Hill, Inc., 1994.
  16. 김기영, 임재호, 김석윤, "반도체 회로 연결선의 신뢰도 해석을 위한 전류 해석 기법," 대한전기학회 논문지 59권 8호, pp. 1406-1415, Aug. 2010.
  17. International Technology Roadmap for Semiconductors (ITRS) : Interconnect, 2007.