The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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A Method of Load Impedance Optimization for High Efficiency Millimeter-wave Range 2nd Harmonic Generation

밀리미터파 대역 제2고조파 고효율 생성을 위한 부하 임피던스의 최적화 방법

  • Received : 2011.02.21
  • Accepted : 2011.07.08
  • Published : 2011.08.01
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Abstract

The objective of this paper is to present a quantitative analysis leading to the assessment of optimum terminating impedances in the design of active frequency multipliers. A brief analysis of the basic principal of the GaAs FET frequency multiplier is presented. The analysis is outlined in bias optimization and drive power determination. Utilizing the equivalent circuit model of GaAs FET, we have simulated the optimized load impedance for the maximum output of the active frequency multipliers. The C-class and reverse C-class frequency doublers have been fabricated and the load impedances have been measured. The experimental results are in good agreement with the estimated results in the simulation with the accuracy of 90%.

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References

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