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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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A Twin Symbol Encoding Technique Based on Run-Length for Efficient Test Data Compression

  • Park, Jae-Seok (Department of Electrical Engineering, Yonsei University) ;
  • Kang, Sung-Ho (Department of Electrical Engineering, Yonsei University)
  • Received : 2010.05.06
  • Accepted : 2010.08.26
  • Published : 2011.02.28
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Abstract

Recent test data compression techniques raise concerns regarding power dissipation and compression efficiency. This letter proposes a new test data compression scheme, twin symbol encoding, that supports block division skills that can reduce hardware overhead. Our experimental results show that the proposed technique achieves both a high compression ratio and low-power dissipation. Therefore, the proposed scheme is an attractive solution for efficient test data compression.

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References

  1. A. Jas et al., "An Efficient Test Vector Compression Scheme Using Selective Huffman Coding," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 22, no. 6, June 2003, pp. 797- 806. https://doi.org/10.1109/TCAD.2003.811452
  2. X. Kavousianos, E. Kalligeros, and D. Nikolos, "Optimal Selective Huffman Coding for Test-Data Compression," IEEE Trans. Computers, vol. 56, no. 8, Aug. 2007, pp. 1146-1152. https://doi.org/10.1109/TC.2007.1057
  3. W. Li et al., "Test Slice Difference Technique for Low Power Encoding," IEEE Int. High Level Design Validation Test Workshop, Nov. 2008, pp. 25-32.
  4. N.A. Touba, "Survey of Test Vector Compression Techniques," IEEE Design Test Mag., vol. 23, no. 4, July 2006, pp. 294-303. https://doi.org/10.1109/MDT.2006.105
  5. A. Chandra and K. Chakrabarty, "System-on-a-Chip Test Data Compression and Decompression Architectures Based on Golomb Codes," IEEE Trans. CAD/ICAS, vol. 20, Mar. 2001, pp. 355-368.
  6. A. Chandra and K. Chakrabarty, "Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression," Proc. IEEE VLSI Test Symp., 2001, pp. 42-47.
  7. A. Jas, J. Ghosh-Dastidar, and N.A. Touba, "Scan Vector Compression/Decompression Using Statistical Coding," Proc. IEEE VLSI Test Symp., Apr. 1999, pp. 114-121.
  8. P. Gonciari, B. Al-Hashimi, and N. Nicolici, "Variable-Length Input Huffman Coding for System-on-a-Chip Test," IEEE Trans. Computer-Aided Design Integ. Circuits Syst., vol. 22, no. 6, June 2003, pp. 783-796. https://doi.org/10.1109/TCAD.2003.811451
  9. M. Nourani and M. Tehranipour, "RL-Huffman Encoding for Test Compression and Power Reduction in Scan Applications," ACM Trans. Design Autom. Electron. Syst., vol. 10, no. 1, Jan. 2005, pp. 91-115, Jan. 2005. https://doi.org/10.1145/1044111.1044117
  10. TetraMax Reference Manual, Dec. 2004, Synopsys Inc., Mountain View, CA, 2001.