JSTS:Journal of Semiconductor Technology and Science

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A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

  • Cho, Kyuik (Dongguk Univ.-Seoul, Dept. of Semiconductor Science) ;
  • Kim, Daeyun (Dongguk Univ.-Seoul, Dept. of Semiconductor Science) ;
  • Song, Minkyu (Dongguk Univ.-Seoul, Dept. of Semiconductor Science)
  • Received : 2012.01.26
  • Published : 2012.12.31
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Abstract

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

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References

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