Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Stable Power Plan Technique for Implementing SoC

SoC 구현을 위한 안정적인 Power Plan 기법

  • Received : 2012.06.13
  • Accepted : 2012.09.09
  • Published : 2012.12.31
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Abstract

ASIC(application specific integrated circuit) process is a set of various technologies for fabricating a chip. Generally there have been many researches for RTL design, synthesis, floor plan & routing, low power scheme, clock tree synthesis, and testability which are widely researched in recent. In this paper we propose a new methodology of power strap routing in basis of design experience and experiment. First the power strap for vertical VDD and VSS and horizontal VDD and VSS is routed, and then after the problems which are generated in this process are analyzed, we propose a new process for resolving them. For this, the strap guide is inserted to protect the unnecessary strap routing and dumped for next steps. Next the unnecessary power straps which are generated the first inserting process are removed, and the pre-routing is performed for the macro cells. Finally the resultant power straps are routed using the dumped routing guide. Through the proposed process we identified the efficient and stable route of the power straps.

ASIC(application specific integrated circuit) 과정은 칩을 제작하기 위한 다양한 기술들의 집합이다. 일반적으로 RTL 설계, 합성, 배치 및 배선, 저전력 기법, 클록 트리 합성, 및 테스트와 같은 대표적인 과정들에 대해서는 많은 연구가 진행 되었고, 지금도 많은 연구가 진행 중이다. 본 논문에서는 이러한 ASIC 방법론에서 전력 플랜과 관련하여 경험적이고 실험적인 전력 스트랩 배선(power strap routing) 방법 기법에 대해서 제안하고자 한다. 먼저 수직 VDD 및 VSS와 수평 VDD 및 VSS를 위한 스트랩의 배선을 수행하고, 이 과정에서 발생하는 문제를 해결하기 위한 기법을 제안한다. 배선 가이드를 생성해서 의도하지 않는 배선을 방지하고, 차후를 위해서 배선 가이드에 대한 정보를 저장한다. 다음으로 불필요한 전력 스트랩을 제거하고, 매크로 핀에 대해 미리 배선을 수행한다. 마지막으로 배선 가이드를 이용하여 최종적인 전력 스트랩 배선을 완료한다. 이러한 과정을 통해서 전력 스트랩이 효율적으로 배선되는 것을 확인하였다.

Keywords

References

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