전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제49권12호
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  • Pages.209-218
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  • 2012
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  • 2287-5026(pISSN)
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  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Field Programmable Stateful Logic Array 패브릭 매핑 및 배치

Fabric Mapping and Placement of Field Programmable Stateful Logic Array

  • 김교선 (인천대학교 전자공학과)
  • Kim, Kyosun (Department of Electronic Engineering, University of Incheon)
  • 투고 : 2012.06.07
  • 발행 : 2012.12.25
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초록

최근 무어의 법칙을 연장시킬 시스템 집적 기술로서 Field Programmable Stateful Logic Array (FPSLA)가 제안되었다. 본 논문은 FPSLA의 설계 자동화 절차를 확립하고 논리 합성, 동기화, 물리적 매핑, 자동 배치 등의 접근 방법을 최초로 제시한다. 특히, 동기화를 통해 배치를 1차원 문제로 축소한 후 비선형 최적화 기법을 개량한 개략 배치 모델 및 하향식 계층적 2분법을 이용한 배치 적법화 알고리즘을 제안하였다. 또한, 제안된 모델 및 알고리즘을 소프트웨어로 구현하여 ACM/SIGDA 벤치 마크 예제에 적용함으로써 그 유효성을 입증하였다. 이 소프트웨어에는 Fanout 수만큼 출력 상태를 같은 단의 멤리스터성 스위치에 복사해야 하는 FPSLA의 특성을 고려하여 최적화 단계 별로 넷을 하이퍼에지로 통합했다가 다시 에지로 분리하는 기법이 제안되었으며 약 18.4%의 추가적 최적화를 이룩했다. FPSLA의 출력 상태 복사는 논리 단 일부에 셀 밀도가 집중되는 문제를 노출했으며 단위 논리 게이트의 Fanin을 제한하는 기법으로 18.5% 감소 효과를 얻었다. FPSLA의 실용성 확보를 위해서는 우선 논리 합성 시 Fanin의 수가 일부 단에 집중되지 않도록 제약하는 방안을 개발하여야 한다. 또한, FPSLA 패브릭 구조를 이식하기 위해 대칭성이 감소된 나노와이어 크로스바가 형성하는 복잡한 그래프 상에서 수행되어야 하는 자동 배선의 효율성 연구도 필요하다. 이러한 툴 개발은 설계 자동화 자체뿐만 아니라 FPSLA의 패브릭 구조 개선에 필요한 실험에 유용한 평가 도구로서도 큰 역할을 할 것이다.

Recently, the Field Programmable Stateful Logic Array (FPSLA) was proposed as one of the most promising system integration technologies which will extend the life of the Moore's law. This work is the first proposal of the FPSLA design automation flow, and the approaches to logic synthesis, synchronization, physical mapping, and automatic placement of the FPSLA designs. The synchronization at each gate for pipelining determines the x-coordinates of cells, and reduces the placement to 1-dimensional problems. The objective function and its gradients for the non-linear optimization of the net length and placement density have been remodeled for the reduced global placement problem. Also, a recursive algorithm has been proposed to legalize the placement by relaxing the density overflow of bipartite bin groups in a top-down hierarchical fashion. The proposed model and algorithm are implemented, and validated by applying them to the ACM/SIGDA benchmark designs. The output state of a gate in an FPSLA needs to be duplicated so that each fanout gate can be connected to a dedicated copy. This property has been taken into account by merging the duplicated nets into a hyperedge, and then, splitting the hyperedge into edges as the optimization progresses. This yields additional 18.4% of the cell count reduction in the most dense logic stage. The practicality of the FPSLA can be further enhanced primarily by incorporating into the logic synthesis the constraint to avoid the concentrated fains of gates on some logic stages. In addition, an efficient algorithm needs to be devised for the routing problem which is based on a complicated graph. The graph models the nanowire crossbar which is trimmed to be embedded into the FPSLA fabric, and therefore, asymmetric. These CAD tools can be used to evaluate the fabric efficiency during the architecture enhancement as well as automate the design.

키워드

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