Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

The New Design Methodology Considering Transistor Layout Variation

트랜지스터 레이아웃 산포를 고려한 새로운 설계 기법

  • Doh, Ji Seong (School of Information & communication Engineering, Sungkyunkwan University) ;
  • Cho, Jun Dong (School of Information & communication Engineering, Sungkyunkwan University)
  • 도지성 (성균관대학교 정보통신공학부) ;
  • 조준동 (성균관대학교 정보통신공학부)
  • Received : 2012.09.19
  • Published : 2012.12.25
Download PDF
⟨ Previous Next ⟩

Abstract

This paper proposes a novel design methodology considering transistor layout variation. The proposed design technique is to improve the transistor's electrical characteristics without performing a circuit simulation to extract transistor layout variation. There are three advantages in the proposed method. Firstly, there is no need to change the normal design flow used in layout designs. Secondly, there is no need to perform simulation in order to extract the transistor layout variation. Thirdly, early warnings in layout design lead to decreasing the number of post layout simulations. Less post layout simulations will decrease the number of iterations in the design cycle and shorten design period. The number of bad transistors in the early design phase were reduced from 17.8% to 2.9% by applying eDRC environment for layout designers to develop Standard Cell Library.

본 논문에서는 소자의 레이아웃 파라미터로 인한 회로 특성 산포를 개선할 수 있는 새로운 설계 기법을 제안한다. 제안된 설계 기법은 회로 시뮬레이션을 수행하지 않고 칩 내에서 레이아웃에 의한 소자의 전기적 특성 분포를 추출하여 불량 소자를 개선하는 방법이다. 이 기법은 3가지 장점이 있다. 첫째, 현 설계 흐름도에 변화를 주지 않아도 된다. 둘째, 레이아웃 설계자가 고비용의 설계 시뮬레이션을 수행하지 않고 소자의 전기적 특성 산포를 추출할 수 있다. 셋째, 초기 레이아웃 설계단계에서 전기적 불량 소자를 찾아 개선하여 설계 기간 단축에 도움이 된다. 제안한 방법에 대한 효율성을 검증하기 위하여 30나노 DRAM 공정에서 총 9종류의 소자 레이아웃 파라미터에 대해서 모델링을 진행하였다. 레이아웃 설계자를 위한 eDRC 환경을 개발하여 Standard Cell Library 설계에 적용하여 초기 설계단계에서 불량 소자 17.8%를 찾아 2.9%로 줄였다.

Keywords

References

  1. G. Scott et al., "NMOS drive current reduction caused by transistor layout and trench isolation induced stress," in Proc. IEDM 1999 Conf., pp. 827-830.
  2. Y. Sheu et al., "Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs," IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 30-38, Jan. 2005.
  3. N. Wils et al., "Influence of STI stress on drain current matching in advanced CMOS," in Proc. ICMTS 2008 Conf., vol. 21, pp. 238-242.
  4. K. W. Su, et al., "A Scaleable Model for STI Mechanical Stress Effect on Layout Dependence of MOS Electrical Characterization,"2003 IEEE CICC, pp. 245-248.
  5. P.G. Drennan, M.L. Kniffin, D.R. Locascio, "Implications of Proximity Effects for Analog Design," Proc. Custom Integrated Circuits Conference, 2006
  6. T. B. Hook, et al., "Lateral Ion Implant Straggle and Mask Proximity Effect," IEEE Trans. Elec. Dev. Sept 2003, pp.1946-1951.
  7. Y. M. Sheu, et al., "Modeling Well Edge Proximity Effect on Highly-Scaled MOSFETs," 2005 IEEE CICC, pp. 831-834.
  8. J. Watts, K.-W. Su, and M. Basel, "Netlisting and modeling well-proximity effects,"IEEE Transactions on Electron Devices, vol. 53, no. 9, pp. 2179-2186, September 2006. https://doi.org/10.1109/TED.2006.880176
  9. M.E. Mason, ''DFM EDA Technology: A Lithographic Perspective,'' Proc. Symp. VLSI Technology, IEEE Press, 2007, pp. 90-91.
  10. K.J. Kuhn, "Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS," Technical Digest IEDM 2007, p. 471 (2007).
  11. J. Wang, A. K. K. Wong, and E. Y. Lam, "Performance optimization for gridded-layout standard cells," in Proc. SPIE 24th Annual BACUS Symposium on Photomask Technology, vol. 5567, December 2004, pp. 107-118.
  12. V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, A. J. Strojwas, and L. Pileggi, "Design methodology for IC manufacturability based on regular logic-bricks," in Proc. 42nd ACM/IEEE Design Automatic Conference (DAC'05), 2005, pp. 353-358.
  13. K. Y. Tong, V. Rovner, L. Pileggi, and V. Kheterpal, "Design methodology of regular logic bricks for robust integrated circuits," in Proc. International Conference on Computer Design (ICCD'06), October 2006.
  14. L. W. Liebmann, A. E. Barish, Z. Baum, H. A. Bonges, S. J. Bukofsky, C. A. Fonseca, S. D. Halle, G. A. Northrop, S. L. Runyon, and L. Sigal, "High-performance circuit design for the RET-enabled 65-nm technology node," in Proc. SPIE Design and Process Integration for Microelectronic Manufacturing II, vol. 5379, May 2004, pp. 20-29.
  15. S. R. Nassif and K. J. Nowka, "Physical design challenges beyond the 22nm node," in Proc. 19th International Symposium on Physical Design (ISPD'10), March 2010, pp. 13-14.
  16. C. Y. C. Hou, "Design challenges and enablement for 28nm and 20nm technology nodes," in Symposium on VLSI Technology (VLSIT'10), June 2010, pp. 225 - 226.
  17. K. Miyamoto, A. Strojwas, E. Hosomi, M. Ooida, H. Ezawa, M. Fukuda, Y. Matsubara, and K. Nu-mata, "Novel circuit design and process technology for leading-edge products," in Symposium on VLSI Technology (VLSIT'10), June 2010, pp. 141-142.
  18. XW Lin, "Layout Proximity Effects and Device Extraction in Circuit Designs", in International Conference on SolidState and Integrated Circuit Technology (ICSICT'08), 2008, pp. 2228-2231.
  19. CC Wang, et al., "Modeling of layout-dependent stress effect in CMOS design", in International Conference on Computer-Aided Design (ICCAD '09), November 2009, pp. 513-520.