Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Consideration of CTS using Efficient Buffer Insertion for SoC in Multiple Clock Domain

다중 클록 영역의 SoC를 위한 효율적인 버퍼삽입 방식의 CTS에 대한 고려

  • Received : 2011.12.13
  • Accepted : 2012.02.03
  • Published : 2012.04.30
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Abstract

In this paper, we consider a clock tree synthesis technique (CTS) based on buffer insertion method in the multiple clock domain. We propose some detail techniques about the preparing items and the practical method for implementing CTS. We also propose a post processing after CTS implementation. Until now, the buffer insertion-based CTS technique has been widely used, and this paper discusses especially it's practical technique to be applied in the commercial fields to develop ASIC and SoC. CTS is very dependent on the used tool. We use Astro of Synopsys and propose the empirical and theoretical information of the detail techniques for implementing CTS using this tool. We expect that the proposed technique becomes to be good guidelines to backend designers.

본 논문에서는 버퍼 삽입 방법에 기반한 다중 클록 영역에서의 클록 트리 합성(clock tree synthesis, CTS) 기법에 대해서 논의한다. CTS를 수행하는데 있어서 준비해야하는 사항들과 실제적인 CTS 수행 방법들에 대해서 세부적인 기술들을 제안한다. 또한 CTS 수행 이후의 후처리 과정에 대해서도 제안한다. 버퍼 삽입 기반의 CTS는 기존에도 사용되는 방법인데 본 논문은 ASIC 및 SoC 상용 작업 현장에서 사용될 수 있는 실전적인 기법들에 대해서 논의하고자 한다. CTS는 사용되는 툴에 매우 의존적인데 본 논문은 Synopsys의 Astro를 대상으로 하였고, 이 툴을 이용하여 CTS를 수행하기 위한 세부적인 기술들에 대해서 이론을 바탕으로 경험적이고 고급적인 기법들을 제안한다. 본 논문을 통해 제안된 기법들은 많은 백앤드(backend) 설계자들에게 좋은 가이드가 될 것으로 기대한다.

Keywords

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