IEMEK Journal of Embedded Systems and Applications (대한임베디드공학회논문지)

Institute of Embedded Engineering of Korea (대한임베디드공학회)
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Analysis on the Effectiveness of the Filter Buffer for Low Power NAND Flash Memory

저전력 NAND 플래시 메모리를 위한 필터 버퍼의 효율성 분석

  • 정보성 (경상대학교 ERI 제어계측공학과) ;
  • 이정훈 (경상대학교 ERI 제어계측공학과)
  • Received : 2012.04.03
  • Accepted : 2012.05.30
  • Published : 2012.08.31
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Abstract

Currently, NAND Flash memory has been widely used in consumer storage devices due to its non-volatility, stability, economical feasibility, low power usage, durability, and high density. However, a high capacity of NAND flash memory causes the high power consumption and the low performance. In the convention memory research, a hierarchical filter mechanism can archive an effective performance improvement in terms of the power consumption. In order to attain the best filter structure for NAND flash memory, we selected a direct-mapped filter, a victim filter, a fully associative filter and a 4-way set associative filter for comparison in the performance analysis. According to the results of the simulation, the fully associative filter buffer with a 128byte fetching size can obtain the bet performance compared to another filter structures, and it can reduce the energy*delay product(EDP) by about 93% compared to the conventional NAND Flash memory.

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References

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