Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Design of High-Reliability eFuse OTP Memory for PMICs

PMIC용 고신뢰성 eFuse OTP 메모리 설계

  • Received : 2012.05.19
  • Accepted : 2012.06.13
  • Published : 2012.07.31
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Abstract

In this paper, a BCD process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose a comparison circuit at program-verify-read mode to test that the program datum is correct by using a dynamic pseudo NMOS logic circuit. The comparison result of the program datum with its read datum is outputted to PFb (pass fail bar) pin. Thus, the normal operation of the designed OTP memory can be verified easily by checking the PFb pin. Also we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a 24-bit eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $289.9{\mu}m{\times}163.65{\mu}m$ ($=0.0475mm^2$).

본 논문에서는 BCD 공정 기반으로 PMIC용 고신뢰성 24비트 듀얼 포트(dual port) eFuse OTP 메모리를 설계하였다. 제안된 dynamic pseudo NMOS 로직회로를 이용한 프로그램 데이터 비교회로는 program-verify-read 모드에서 프로그램 데이터와 read 데이터를 비교하여 PFb(pass fail bar) 핀으로 비교 결과를 출력한다. 그래서 한 개의 PFb 핀만 테스트하므로 eFuse OTP 메모리가 정상적으로 프로그램 되었는지를 확인할 수 있다. 그리고 program-verify-read 모드를 이용하여 프로그램된 eFuse 저항의 변동을 고려한 가변 풀-업 부하(variable pull-up load)를 갖는 센싱 마진 테스트 회로를 설계하였다. Magnachip $0.35{\mu}m$ BCD 공정을 이용하여 설계된 24비트 eFuse OTP 메모리의 레이아웃 면적은 $289.9{\mu}m{\times}163.65{\mu}m$($=0.0475mm^2$)이다.

Keywords

References

  1. S. H. Kulkarni et al., "A 4kb metal-fuse OTP-ROM macro featuring a 2V programmable 1.37${\mu}m$2 1T1R bit cell in 32nm high-k metal-gate CMOS," IEEE Solid-State Circuits, vol. 45, no. 4, pp. 863-868, April 2010 https://doi.org/10.1109/JSSC.2010.2040115
  2. J. Safran, A. Leslie, et al., "A compact eFuse programmable array memory for SOI CMOS," Symposium on VLSI Circuits, pp. 72-73, June 2007.
  3. N. Robson et al., "Electrically programmable fuse (eFuse): From memory redundancy to autonomic chip," Proceedings of Custom Integrated Circuits Conference, pp. 799-804, Sep. 2007.
  4. M. Alavi et al., "A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process," IEEE International Electron Devices Meeting, pp. 855-858, Dec. 1997.
  5. J. H. Kim et al., "Design of 1-Kb eFuse OTP memory IP with reliability considered," Journal of Semiconductor Technology and Science, vol. 11, no. 2, pp. 88-94, June, 2011. https://doi.org/10.5573/JSTS.2011.11.2.088
  6. J. H. Jang et al., "Design of an 8-bit differential paired eFuse OTP memory IP reducing sensing resistance," J. Cent. South Univ., vol. 19, no. 1, pp. 168-173, January 2012. https://doi.org/10.1007/s11771-012-0987-4

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  3. Power IC용 저면적 Differential Paired eFuse OTP 메모리 설계 vol.8, pp.2, 2012, https://doi.org/10.17661/jkiiect.2015.8.2.107
  4. PMIC용 저면적 Dual Port eFuse OTP 메모리 IP 설계 vol.8, pp.4, 2012, https://doi.org/10.17661/jkiiect.2015.8.4.310