대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

파워게이팅과 전압레벨조절을 이용하여 누설전류를 줄인 SRAM

A Low Leakage SRAM Using Power-Gating and Voltage-Level Control

  • 양병도 (충북대학교 전자정보대학) ;
  • 천유소 (충북대학교 전자정보대학)
  • Yang, Byung-Do (College of Electrical and Computer Engineering, Chungbuk National University) ;
  • Cheon, You-So (College of Electrical and Computer Engineering, Chungbuk National University)
  • 투고 : 2012.05.31
  • 심사 : 2012.07.16
  • 발행 : 2012.08.25
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초록

본 논문에서는 파워게이팅과 전압레벨조절을 이용하여 누설전류를 줄인 SRAM을 제안하였다. 제안된 파워게이팅 기법은 데이터를 저장하지 않은 메모리 셀 블록의 전력공급을 차단함으로써 누설전류를 크게 감소시키고, 제안된 전압레벨조절 기법은 데이터가 저장된 메모리 셀 블록의 접지전압을 올림으로써 누설전류를 줄여준다. $4K{\times}8$비트 SRAM 칩은 $0.13{\mu}m$ CMOS 공정으로 제작되었고 VDD=1.2V로 동작하였다. 메모리 사용률이 0~100%에 대하여, 동작 모드에서의 누설전류는 $1.23{\sim}9.87{\mu}W$이고 대기 모드에서 누설전류는 $1.23{\sim}3.01{\mu}W$였다. 대기 모드 동안에, 제안된 SRAM의 누설전류는 기존의 SRAM의 12.5~30.5%로 감소하였다.

This letter proposes a low-leakage SRAM using power-gating and voltage-level control. The power-gating scheme significantly reduces leakage power by shutting off the power supply to blank memory cell blocks. The voltage-level control scheme saves leakage power by raising the ground line voltage of SRAM cells and word line decoders in data-stored memory cell blocks. A $4K{\times}8bit$ SRAM chip was fabricated using a 1.2V $0.13{\mu}m$ CMOS process. The leakage powers are $1.23{\sim}9.87{\mu}W$ and $1.23{\sim}3.01{\mu}W$ for 0~100% memory usage in active and sleep modes, respectively. During the sleep mode, the proposed SRAM consumes 12.5~30.5% leakage power compared to the conventional SRAM.

키워드

참고문헌

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