대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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H.264/AVC 를 위한 높은 처리량의 2-D $8{\times}8$ integer transforms 병렬 구조 설계

High Throughput Parallel Design of 2-D $8{\times}8$ Integer Transforms for H.264/AVC

  • Sharma, Meeturani (Department of Electronic Engineering, Konkuk University) ;
  • Tiwari, Honey (Department of Electronic Engineering, Konkuk University) ;
  • Cho, Yong-Beom (Department of Electronic Engineering, Konkuk University)
  • 투고 : 2012.05.31
  • 심사 : 2012.07.25
  • 발행 : 2012.08.25
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초록

본 논문에서 H.264표준을 위해 2차원 $8{\times}8$ 순방향/역방향 정수 DCT 변환을 빠르고 효율적으로 계산할 수 있는 알고리즘을 제안한다. 순방향/역방향 변환은 간단한 시프트와 덧셈 동작을 사용하여 계산 복잡도를 줄였으며, DCT 연산에 메모리를 사용하지 않으므로 해서 불필요한 자원소모를 줄였다. 제안된 파이프라인 아키텍처의 최대 동작 주파수는 1.184GHz이며, 합성결과는 44864 게이트가 사용되어 25.27Gpixels/sec의 스루풋을 보여준다. 면적 비율에 비해 높은 스루풋으로 인해, 제안된 설계는 H.264/AVC 고해상도 비디오기술의 실시간 처리에 효율적으로 사용할 수 있다.

In this paper, the implementation of high throughput two-dimensional (2-D) $8{\times}8$ forward and inverse integer DCT transform for H.264 is presented. The forward and inverse transforms are represented using simple shift and addition operations. Matrix decomposition and matrix operation such as the Kronecker product and direct sum are used to reduce the computation complexity. The proposed design uses integer computations and does not use transpose memory and hence, the resource consumption is also reduced. The maximum operating frequency of the proposed pipelined architecture is 1.184 GHz, which achieves 25.27 Gpixels/sec throughput rate with the hardware cost of 44864 gates. High throughput and low hardware makes the proposed design useful for real time H.264/AVC high definition processing.

키워드

참고문헌

  1. T. Wiegand and G. Sullivan, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T rec. H.264/ISO/IEC 14496-10 AVC, presented at Joint Video Team (JVC) of ISO/IEC MPEG and ITU-T VCEG), 2003.
  2. I.E.G. Richardson, H.264 and MPEG-4 Video Compression - Video Coding for Next-generation Multimedia, John Wiley & Sons Ltd., 2003.
  3. H.S. Malvar, A. Hallapuro, M. Karczewicz, and L. Kerofsky, "Low complexity transform and quantization in H.264/AVC," IEEE Trans. Circuits Syst. Video Technol., vol.13, no.7, pp.598-603, July 2003. https://doi.org/10.1109/TCSVT.2003.814964
  4. S. Gordon, D. Marple, and T. Wiegand, "Simplified use of $8{\times}8$ transforms-Updated proposal and results," in Proc. JVT-K028, 11th Meeting, Munich, Germany, Mar. 2004.
  5. A. Madisetti and A. N. Willson, "A 100 MHz 2-D $8{\times}8$ DCT/IDCT processor for HDTV applications," IEEE Trans. Circuits Syst. Video Technol., vol. 5, pp. 158-165, Apr. 1995. https://doi.org/10.1109/76.388064
  6. S. Uramoto et al., "A 100-MHz 2-D discrete cosine transform core processor," IEEE J. Solid-State Circuits, vol. 27, pp. 492-498, Apr. 1992. https://doi.org/10.1109/4.126536
  7. Guo-An Su and Chih-Peng Fan, "Low-Cost Hardware-Sharing Architecture of Fast 1-D Inverse Transforms for H.264/AVC and AVS Applications," IEEE Trans. on Circuits and Systems-II: EXPRESS BRIEFS, vol. 55, NO. 12, pp. 1249-1253, December, 2008. https://doi.org/10.1109/TCSII.2008.2008058
  8. Y. P. Lee, T. H. Chen, L. G. Chen, M. J. Chen, and C. W. Ku, "A cost effective architecture for $8{\times}8$ two-dimensional DCT/IDCT using direct method," IEEE Trans. Circuits Syst. Video Technol., vol. 7, pp. 459-467, June 1997. https://doi.org/10.1109/76.585925
  9. Y.-M. Huang and J.-L.Wu, "A refined fast 2-D discrete cosine transform algorithm," IEEE Trans. Signal Processing, vol. 47, pp. 904-907, Mar. 1999. https://doi.org/10.1109/78.747801
  10. C. P. Fan, "Fast 2-dimensional $8{\times}8$ integer transform algorithm design for H.264/AVC fidelity range extensions," IEICE Trans. Inf. Syst., vol. E89-D, pp. 3006-3011, Dec. 2006. https://doi.org/10.1093/ietisy/e89-d.12.3006
  11. C. P. Fan and Y. L. Lin, "Implementations of low-cost hardware sharing architectures for fast $8{\times}8$ and $4{\times}4$ integer transforms in H.264/AVC," IEICE Trans. Fundamentals, vol. E90-A, no. 2, Feb. 2007.
  12. Woong Hwangbo and Chong-Min Kyung, "A Multi-Transform Architecture for H.264/AVC High-Profile Coders", IEEE Trans. on Multimedia, Vol.12, No.3, Apr. 2010.
  13. R.A. Horn and C.R. Johnson, Topics in Matrix Analysis, pp.239-267, Cambridge Univ. Press, New York, 1991.
  14. C. P. Fan, "Cost-effective hardware sharing architectures of fast $8{\times}8$ and $4{\times}4$ integer transforms for H.264/AVC," in Proc. IEEE Asia Pacific Conf. Circuits and Systems, Dec. 2006, pp. 776-779.
  15. Y. C. Chao, H. H. Tsai, Y. H. Lin, J. F. Yang, and B. D. Liu, "A novel design for computation of all transforms in H.264/AVC decoders," in Proc. IEEE Int. Conf. Multimedia and Expo, Jul. 2007, pp. 1914-1917.
  16. Y. Li, Y. He, and S. Mei, "A highly parallel joint VLSI architecture for transforms in H.264/AVC," J. Signal Process. Syst., vol. 50, pp. 19-32, Oct. 2007.
  17. G. Pastuszak, "Transforms and quantization in the high-throughput H.264/AVC encoder based on advanced mode selection," in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, Apr. 2008, pp. 203-208.
  18. C. Y. Huang, L. F. Chen, and Y. K. Lai, "A high-speed 2-D transform architecture with unique kernel for multi-standard video applications," in Proc. IEEE Int. Symp. Circuits and Systems, May 2008, pp. 21-24.
  19. Meeturani Sharma, Honey Durga Tiwari, Yong Beom Cho, "High throughput parallel design of 2-D $8{\times}8$ integer transforms for H.264/AVC", SoC Conference, Seoul, April, 2012.