Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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1V 1.6-GS/s 6-bit Flash ADC with Clock Calibration Circuit

클록 보정회로를 가진 1V 1.6-GS/s 6-bit Flash ADC

  • Received : 2012.07.24
  • Accepted : 2012.08.13
  • Published : 2012.09.30
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Abstract

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

클록 보정회로를 가진 1V 1.6-GS/s 6-비트 flash 아날로그-디지털 변환기 (ADC: analog-to-digital converter)가 제안된다. 1V의 저전압에서 고속 동작의 입력단을 위해 bootstrapped 아날로그 스위치를 사용하는 단일 track/hold 회로가 사용되며, 아날로그 노이즈의 감소와 고속의 동작을 위해 평균화 기법이 적용된 두 단의 프리앰프와 두 단의 비교기가 이용된다. 제안하는 flash ADC는 클록 보정회로에 의해 클록 duty cycle과 phase를 최적화함으로 flash ADC의 동적특성을 개선한다. 클록 보정 회로는 비교기를 위한 클록의 duty cycle을 제어하여 evaluation과 reset 시간을 최적화한다. 제안된 1.6-GS/s 6-비트 flash ADC는 1V 90nm의 1-poly 9-metal CMOS 공정에서 제작되었다. Nyquist sampling rate인 800 MHz의 아날로그 입력신호에 대해 측정된 SNDR은 32.8 dB이며, DNL과 INL은 각각 +0.38/-0.37 LSB, +0.64/-0.64 LSB이다. 구현된 flash ADC의 면적과 전력소모는 각각 $800{\times}500{\mu}m2$와 193.02 mW 이다.

Keywords

References

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