Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Design of Parallel Decimal Floating-Point Arithmetic Unit for High-speed Operations

고속 연산을 위한 병렬 구조의 십진 부동소수점 연산 장치 설계

  • Yun, Hyoung-Kie (Department of Information and Communication Engineering, Hoseo University) ;
  • Moon, Dai-Tchul (Department of Information and Communication Engineering, Hoseo University)
  • Received : 2013.10.01
  • Accepted : 2013.11.25
  • Published : 2013.12.31
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Abstract

In this paper, a decimal floating-point arithmetic unit(DFP) was proposed and redesigned to support high speed arithmetic operation employed parallel processing technique. The basic architecture of the proposed DFP was based on the L.K.Wang's DFP and improved it enabling high speed operation by parallel processing for two operands with same size of exponent. The proposed DFP was synthesized as a target device of xc2vp30-7ff896 using Xilinx ISE and verified by simulation using Flowrian tool of System Centroid co. Compared to L.K.Wang's DFP and reference [6]'s method, the proposed DFP improved data processing speed about 8.4% and 3% respectively in case of same input data.

본 논문에서 제안된 십진 부동소수점 연산 장치(decimal floating-point arithmetic unit, DFP)는 L.K.Wang에 의해 제안된 십진 부동소수점 유닛을 기반으로 하여 데이터의 병렬 처리를 통해 동일한 크기의 지수를 갖는 두 오퍼랜드의 가수 영역의 고속 연산을 지원하도록 재설계 하였다. 제안된 십진 부동소수점 연산 장치는 Xilinx ISE를 이용하여 xc2vp30-7ff896 타겟 디바이스로 합성하였으며 (주)시스템센트로이드의 Flowrian을 통해 시뮬레이션 검증하였다. 제안된 방식은 L.K.Wang에 의해 제안된 설계 방식 및 참고문헌 [6]의 설계 방식과 비교하여 동일한 입력 데이터를 이용하여 시뮬레이션 검증한 결과, L.K.Wang 방식보다 약 8.4%, 참고문헌 [6]의 방식보다 약 3% 정도의 처리 속도가 향상되었다.

Keywords

References

  1. IEEE, IEEE 754-2008 Standard for Floating-Point Arithmetic, 2008.
  2. Lipsa Sahu, Ruby Dev, "An Efficient IEEE 754 Compliant FPU using verilog", Department of Computer Science and Engineering National Institute of Technology Rourkela, 2012.
  3. Jong-Hyeon Kim, Parallel Computer Architecture, New ed. Saeng-Neung Publish. 2010. 10.
  4. L. K. Wang, C. Tsen, M. J. Schulte, and D. Jhalani, "Benchmarks and Performance Analysis of Decimal Floating-Point Applications", Computer Design, ICCD 2007. 25th International Conference on, pp. 164-170, 2007.
  5. Hickmann, B., Krioukov A., Schulte M., Erle M., "A parallel IEEE P754 decimal floating-point multiplier", Computer Design, ICCD 2007. 25th International Conference on, pp. 296-303, 2007. 10.
  6. Steven Carlough, Adam Collura, Silvia Mueller, Michael Kroener, "The IBM zEnterprise-196 Decimal Floating-Point Accelerator", Computer Arithmetic (ARITH), 2011 20th IEEE Symposium on, PP. 139 - 146, 2011.
  7. Chang-Ho Lee, Ji-Won Kim, In-Guk Hwang, and Sang- Bang Choi, "Design of Dual-Path Decimal Floating-Point Adder", IEEK Journal, No. 49(9), pp. 183-195, 2012. 9. https://doi.org/10.5573/ieek.2012.49.9.183

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  1. 선행 제로 예측기를 이용한 고속 연산 십진 부동소수점 가산기 설계 vol.19, pp.2, 2013, https://doi.org/10.6109/jkiice.2015.19.2.407