The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Design of Core Chip for 3.1Gb/s VCSEL Driver in 0.18㎛ CMOS

0.18㎛ CMOS 3.1Gb/s VCSEL Driver 코아 칩 설계

  • 양충열 (한국전자통신연구원 광인터넷연구부, 광액세스연구팀) ;
  • 이상수 (한국전자통신연구원 광인터넷연구부, 광액세스연구팀)
  • Received : 2012.10.26
  • Accepted : 2013.01.02
  • Published : 2013.01.31
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Abstract

We propose a novel driver circuit design using $0.18{\mu}m$ CMOS process technology that drives a 1550 nm high-speed VCSEL used in optical transceiver. We report a distinct improvement in bandwidth, voltage gain and eye diagram at 3.1Gb/s data rate in comparison with existing topology. In this paper, the design and layout of a 3.1Gb/s VCSEL driver for optical transceiver having arrayed multi-channel of integrating module is confirmed.

본 논문에서는 $0.18{\mu}m$ CMOS 공정 기술을 이용하여 광트랜시버에 사용된 1550 nm 고속 VCSEL을 구동하는 드라이버 회로를 제안한다. 3.1Gb/s 데이터 속도에서 기존 구조에 비하여 향상된 대역폭, 이득 및 아이 다이어그램을 확인하였다. 본 논문에서는 다중채널 어레이 집적모듈을 갖는 광트랜시버에 응용하기 위한 3.1Gb/s VCSEL 드라이버의 설계 및 레이아웃을 확인한다.

Keywords

References

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