전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제50권1호
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  • Pages.131-136
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  • 2013
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  • 2287-5026(pISSN)
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  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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TSV 기반 3D IC Pre/Post Bond 테스트를 위한 IEEE 1500 래퍼 설계기술

IEEE 1500 Wrapper Design Technique for Pre/Post Bond Testing of TSV based 3D IC

  • Oh, Jungsub (LIG Nex1) ;
  • Jung, Jihun (Department of Computer Science & Engineering, Hanyang University) ;
  • Park, Sungju (Department of Computer Science & Engineering, Hanyang University)
  • 투고 : 2012.08.09
  • 발행 : 2013.01.25
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⟨ 이전 논문 다음 논문 ⟩

초록

칩 적층기술의 발달로 TSV(Through Silicon Via) 기반 3D IC가 개발되었다. 3D IC의 높은 신뢰성과 수율을 얻기 위해서는 pre-bond 와 post-bond 수준에서 다양한 TSV 테스트가 필수적이다. 본 논문에서는 pre-bond 다이의 TSV 연결부에서 발생하는 미세한 고장과 post-bond 적층된 3D IC의 TSV 연결선에서 발생하는 다양한 고장을 테스트할 수 있는 설계기술을 소개한다. IEEE 1500 표준 기반의 래퍼셀을 보완하여 TSV 기반 3D IC pre-bond 및 post-bond의 at speed test를 통하여 known-good-die와 무결점의 3D IC를 제작하고자 한다.

TSV based 3D ICs have been widely developed with new problems at die and IC levels. It is imperative to test at post-bond as well as pre-bond to achieve high reliability and yield. This paper introduces a new testable design technique which not only test microscopic defects at TSV input/output contact at a die but also test interconnect defects at a stacked IC. IEEE 1500 wrapper cells are augmented and through at-speed tests for pre-bond die and post-bond IC, known-good-die and defect free 3D IC can be massively manufactured+.

키워드

참고문헌

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