Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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A Design of Multi-Standard LDPC Decoder for WiMAX/WLAN

WiMAX/WLAN용 다중표준 LDPC 복호기 설계

  • 서진호 (금오공과대학교 전자공학부) ;
  • 박해원 (금오공과대학교 전자공학부) ;
  • 신경욱 (금오공과대학교 전자공학부)
  • Received : 2012.11.16
  • Accepted : 2012.12.11
  • Published : 2013.02.28
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Abstract

This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.

본 논문에서는 IEEE 802.16e 모바일 WiMAX 표준의 19가지 블록길이(576~2304)에 따른 6가지 부호율(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6)과 IEEE 802.11n WLAN 표준의 3가지 블록길이(648, 1296, 1944)에 따른 4가지 부호율(1/2, 2/3, 3/4, 5/6)을 지원하는 다중표준 LDPC 복호기를 설계하였다. Layered 복호방식의 블록-시리얼(부분병렬) 구조와 SM(sign-magnitude) 수체계 기반의 DFU(decoding function unit)를 적용하여 하드웨어 복잡도를 최소화시켰다. 설계된 회로는 FPGA 구현을 통해 하드웨어 동작을 검증하였으며, 0.13-${\mu}m$ CMOS 셀 라이브러리로 합성한 결과 약 312,000 게이트와 70,000 비트의 메모리로 구현되었고, 100 MHz@1.8V로 동작하여 79~210 Mbps의 성능을 갖는 것으로 평가되었다.

Keywords

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