JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Efficient Overlapped LDPC Decoder with a Upper Dual-diagonal Structure

  • Byun, Yong Ki (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Park, Jong Kang (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kwon, Soongyu (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Jong Tae (School of Information and Communication Engineering, Sungkyunkwan University)
  • Received : 2012.04.27
  • Published : 2013.02.28
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Abstract

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

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References

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