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Efficient Switching Pattern to Decrease Switching Losses in Cascaded H-bridge PWM Multilevel Inverter

Cascaded H-bridge PWM 멀티레벨인버터의 스위칭 손실 저감을 위한 효율적인 스위칭 패턴

  • Jeong, Bo Chang (Dept. of Electronics and Control Engineering, Hanbat National University) ;
  • Kim, Sun-Pil (Dept. of Electrical Engineering, Chonnam National University) ;
  • Kim, Kwang Soo (Dept. of Electronics and Control Engineering, Hanbat National University) ;
  • Park, Sung-Jun (Dept. of Electrical Engineering, Chonnam National University) ;
  • Kang, Feel-Soon (Dept. of Electronics and Control Engineering, Hanbat National University)
  • Received : 2012.11.16
  • Accepted : 2013.03.25
  • Published : 2013.04.01

Abstract

It presents an efficient switching pattern, which expects a reduction of switching losses in a cascaded H-bridge PWM multilevel inverter. By the proposed switching scheme, the lower H-bridge module operates at low frequency of 60[Hz] because it assigns to transfer most load power. The upper H-bridge module operates at high frequency of PWM switching to improve THD of output voltage. The proposed switching pattern applies to cascaded H-bridge multilevel inverter with PD, APOD, bipolar, and unipolar switching methods. By computer-aided simulations, we verify the validity of the proposed switching scheme. Finally, we prove that the proposed PD and APOD switching patterns are better than those of the conventional one in efficiency.

Keywords

References

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