The Journal of Korean Institute of Electromagnetic Engineering and Science (한국전자파학회논문지)

The Korean Institute of Electromagnetic Engineering and Science (한국전자파학회)
권호 표지
DOI QR코드

DOI QR Code

Design of a V Band Power Amplifier Using 65 nm CMOS Technology

65 nm CMOS 공정을 이용한 V 주파수대 전력증폭기 설계

  • Lee, Sungah (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Cui, Chenglin (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Seong-Kyun (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Byung-Sung (College of Information and Communication Engineering, Sungkyunkwan University)
  • ;
  • ;
  • 김성균 (성균관대학교 정보통신대학) ;
  • 김병성 (성균관대학교 정보통신대학)
  • Received : 2013.01.09
  • Accepted : 2013.03.05
  • Published : 2013.04.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this work, a CMOS two stage differential power amplifier which includes Marchand balun, transformer and injection-locked buffer is presented. The power amplifier is targeted for 70 GHz frequency band and fabricated using 65 nm technology. The measurement results show 8.5 dB maximum voltage gain at 71.3 GHz and 7.3 GHz 3 dB bandwidth. The measured maximum output power is 8.2 dBm, input $P_{1dB}$ is -2.8 dBm, output $P_{1dB}$ is 4.6 dBm and maximum power added efficiency is 4.9 %. The power amplifier consumes 102 mW DC power from 1.2 V supply voltage.

본 논문에서는 Marchand 발룬, 트랜스포머와 주입 잠금 버퍼를 이용한 CMOS 2단 차동전력증폭기를 보여준다. 본 전력증폭기는 70 GHz 주파수 대역을 목표로 설계하였고, 65 nm 공정을 이용하여 제작하였다. 측정 결과, 71.3 GHz에서 8.5 dB의 최대 전압 이득과 7.3 GHz의 3 dB 대역폭을 얻었다. 측정된 최대 출력 전력은 8.2 dBm, 입력 $P_{1dB}$는 -2.8 dBm, 출력 $P_{1dB}$는 4.6 dBm이며, 최대 전력 부가 효율은 4.9 %이다. 본 전력증폭기는 1.2 V의 전원으로부터 102 mW의 DC 전력을 소모한다.

Keywords

References

  1. T. Suzuki, Y. Kawano, M. Sato, T. Hirose, and K. Joshin, "60 and 77 GHz power amplifiers in standard 90 nm CMOS", in IEEE Int., Solid-Stae Circuits Conf. Tech. Dig., pp. 562-563, Feb. 2008.
  2. Y. Hamada, M. Tanomura, M. Ito, and K. Maruhashi, "A high gain 77 GHz power amplifier operating at 0.7 V based on 90 nm CMOS technology", in IEEE Radio Freq. Integr. Circuits (RFIC) Symp. Dig., pp. 39-42, Jan. 2009.
  3. J. -J. Kuo, W. -H. Lin, C. -C. Kuo, J. R. Tseng, Z. -M. Tsai, K- Y. Lin, and H. Wang, "A 71-76 GHz chip set for wireless communication in 65-nm CMOS technology", in IEEE MTT-S Int. Microw. Symp. Dig., pp. 189-192, Jun. 2009.
  4. Y. Li, M. Hung, S. Huang, and J. Lee, "A fully integrated 77 GHz FMCW radar system in 65 nm CMOS", in IEEE Int., Solid-Stae Circuits Conf. Tech. Dig., pp. 216-217, Feb. 2010.
  5. S. Aloui, E. Kerherve, R. Plana, and D. Belot, "RFpad, transmission lines and balun optimization for 60 GHz 65 nm CMOS power amplifier", in IEEE Radio Freq. Integr. Circuits (RFIC) Symp. Dig., pp. 211-214, May 2010.
  6. J. X. Liu, C. -Y. Hsu, H. - R. Chuang, and C. -Y. Chen, "A 60-GHz Millimeter-wave CMOS machand balun", in IEEE Radio Freq. Integr. Circuits (RFIC) Symp. Dig., pp. 445-448, Jun. 2007.
  7. B. Heydari, M. Bohsali, E. Adabi, and A. M. Niknejad, "A 60 GHz power amplifier in 90 nm CMOS technology", in Proc. IEEE CICC, pp. 769-772, Sep. 2007.
  8. W. L. Chan, J. R. Long, M. Spirito, and J. J. Pekarik, "A 60 GHz-band 1 V 11.5 dBm power amplifier with 11 % PAE in 65 nm CMOS", in IEEE Int., Solid-Stae Circuits Conf. Tech. Dig., pp. 380-381, 381a, Feb. 2009.
  9. S. C. Cripps, RF Power Amplifiers for Wireless Communications, Artech House, pp. 20-36, 1999.
  10. G. Gonzalez, Microwave Transistor Amplifiers Analysis and Design, Prentice Hall, pp. 217-228, 1997.