Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

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Primitive IPs Design Based on a Memristor-CMOS Circuit Technology

멤리스터-CMOS 회로구조 기반의 프리미티브 IP 설계

  • Han, Ca-Ram (College of Electrical and Computer Engineering, Chungbuk National University) ;
  • Lee, Sang-Jin (College of Electrical and Computer Engineering, Chungbuk National University) ;
  • Eshraghian, Kamran (College of Electrical and Computer Engineering, Chungbuk National University) ;
  • Cho, Kyoungrok (College of Electrical and Computer Engineering, Chungbuk National University)
  • 한가람 (충북대학교 전자정보대학) ;
  • 이상진 (충북대학교 전자정보대학) ;
  • ;
  • 조경록 (충북대학교 전자정보대학)
  • Received : 2013.01.02
  • Published : 2013.04.25
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Abstract

This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Memristor-CMOS and is verified with SPICE-like Memristor model under $0.18{\mu}m$ CMOS technology. As a result, an example design Memristor-CMOS full adder has only 47.6 % of silicon area compare to the CMOS full-adder.

본 논문에서는 멤리스터 기반의 논리 게이트와 멤리스터-CMOS 기반의 프리미티브 IP 설계 방법을 제안하였다. 회로 설계를 위한 멤리스터 모델을 제시하고 멤리스터의 AND 및 OR 연결을 기본으로 멤리스터-CMOS 회로설계를 위한 프리미티브 IP설계 방법을 제안하였고, $0.18{\mu}m$ CMOS 공정과 멤리스터 SPICE 모델을 이용한 시뮬레이션을 통해 검증되었다. 회로는 멤리스터와 CMOS 결합을 하여 레이아웃 설계를 하고 네트리스트를 추출하였다. 디지털 프리미티브 IP들에 대해 기존의 CMOS와 면적비교를 수행하였으며, 멤리스터-CMOS 전가산기는 CMOS 전가산기에 비하여 47.6 %의 면적이 감소되었다.

Keywords

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