Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Manufacturing yield challenges for wafer-to-wafer integration

Wafer-to-Wafer Integration을 위한 생산수율 챌린지에 대한 연구

  • Received : 2013.02.21
  • Accepted : 2013.03.22
  • Published : 2013.03.30
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Abstract

Wafer-to-Wafer (W2W) integration technology is an emerging technology promising many benefits, such as reduced size, improved performance, reduced power, lower cost, and divergent integration. As the maturity of W2W technology progresses, new applications will become more viable. However, at present the cost for W2W integration is still very high and both manufacturing yield and reliability issues have not been resolved yet for high volume manufacturing (HVM). Especially for WTW integration resolving compound yield issue can be a key factor for HVM. To have the full benefits of WTW integration technology more than simple wafer stacking technologies are necessary. In this paper, the manufacturing yield for W2W integration is described and the challenges of WTW integration will be discussed.

3D integration 기술 특히 W2W integration 기술은 전자산업의 디바이스 scaling 문제를 해결하고 고성능화 소형화 추세에 맞춘 가장 핵심적인 기술 방향이다. 그러나 W2W integration 기술은 현재 가격과 생산수율의 장애를 가지고 있고, 이를 해결하기 위해서 웨이퍼 매칭, 리던던시, 다이 면적 축소, 배선 층 수 축소와 같은 디자인 연구들이 진행되고 있다. W2W integration 기술이 대량생산으로 연결되기 위해서는 우선적으로 웨이퍼 본딩, 실리콘연삭, TSV 배선 공정의 최적화가 이루어져야 하겠지만, 가격을 포함한 생산수율을 높이기 위해서는 반드시 디자인 연구가 선행되어야 하겠다.

Keywords

References

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