Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지
DOI QR코드

DOI QR Code

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and 2nd-order RC filter

2차-RC 필터와 Sample-Hold 커패시터로 구성된 루프 필터와 단방향 전하펌프를 가진 PLL

  • Received : 2013.06.10
  • Accepted : 2013.08.02
  • Published : 2013.10.31
Download PDF
⟨ Previous Next ⟩

Abstract

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and 2nd-order RC filter has been proposed. The goal of the proposed PLL is the suppression of reference spur which is caused by charge pump mismatch. It also improves phase noise characteristic. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

이 논문에서는 2차-RC 필터와 sample-hold 커패시터로 구성된 루프필터와 단방향 전하펌프를 가진 위상고정루프를 제안하였다. 제안된 위상고정루프의 목적은 전하펌프의 전류 불일치에 의한 기준 신호 의사 잡음을 개선 한다는 것이다. 또한 이를 통하여 위상 잡음 특성도 개선하였다. 회로는 1.8V $0.18{\mu}m$ CMOS 공정의 파라미터를 이용하여 HSPICE로 시뮬레이션을 수행하였고 회로의 동작을 검증하였다.

Keywords

References

  1. Marianne M. Kamal, Emad W. El-Shewekh, and Muhammad H. El-Saba, "Design and implementation of a low-phase-noise integrated CMOS Frequency Synthesizer for high-sensitivity narrow-band FM transceivers," Microelectronics, pp. 167-175, Cairo, Egypt. Dec. 2003.
  2. Yan Ge, Wennan Feng, Zhongjian Chen, Song Jia and Lijiu Ji, "A Fast Locking Charge-Pump PLL with Adaptive Bandwidth," ASIC. vol. 1, ASICON, pp. 431-434, Oct. 2005.
  3. Kyoohyun Lim, Chan-Hong Park, Dal-Soo Kim and Beomsup Kim, "A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 807-815, June. 2000. https://doi.org/10.1109/4.845184
  4. Tsung-Hsien Lin and William J. Kaiser, "A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 424-431, March. 2001. https://doi.org/10.1109/4.910481
  5. Wu-Hsin Chen, Wing-Fai Loke, and Byunghoo Jung, "A 0.5-V, 440-μ W Frequency Synthesizer for Implantable Medical Devices," IEEE J.Solid-State Circuits, vol. 47, no. 8, pp. 1896-1907, August 2012. https://doi.org/10.1109/JSSC.2012.2196315
  6. Shen Ye, Lars Jansson and Ian Galton, "A Multiple-Crystal Interface PLL With VCO Realignment to Reduce Phase Noise," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1795-1803, December. 2002. https://doi.org/10.1109/JSSC.2002.804339
  7. Te-Wen Liao, Chia-Min Chen, Jun-Ren, and Chung-Chih Hung, "Random Pulsewidth Matching Frequency Synthesizer With Sub-Sampling Charge Pump," IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 59, no. 12, pp. 2815-2824, December. 2012. https://doi.org/10.1109/TCSI.2012.2206462
  8. E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, "A 700-kHz bandwidth ${\Sigma}{\Delta}fractional$ synthesizer with spur compensation and linearization techniques," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1446-1454, Sep. 2004. https://doi.org/10.1109/JSSC.2004.831598
  9. S. Pamariti, L. Jansson, and I. Galton, "A wideband 2.4-GHz delta-sigma fractional-N PLL with 10Mb/s in loop modulation," IEEE J. Solid-State Circuit, vol. 39, no. 1, pp. 49-62, Jan. 2004. https://doi.org/10.1109/JSSC.2003.820858
  10. F. M. Gardner, Phaselock Techniques. Hoboken, NJ: Wiley, 2005
  11. Y. G. Song and, Y. S. Choi, "A Fast Locking Phase Locked Loop with Multiple Charge Pumps", IEEK-SD, vol. 46, no. 2, pp. 71-77, Feb. 2009.
  12. H. C. Luong and G. C. T. Leung, Low-Voltage CMOS RF Frequency Synthesizers. Cambridge: Cambridge.