전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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전 병렬구조 기반 8.1 Gbps 고속 및 다중 모드 QC-LDPC 복호기

8.1 Gbps High-Throughput and Multi-Mode QC-LDPC Decoder based on Fully Parallel Structure

  • 정용민 (연세대학교 전기전자공학과) ;
  • 정윤호 (한국항공대학교 항공전자공학과) ;
  • 이성주 (세종대학교 정보통신공학과) ;
  • 김재석 (연세대학교 전기전자공학과)
  • Jung, Yongmin (School of Electrical and Electronic Engineering, Yonsei University) ;
  • Jung, Yunho (School of Electronics, Telecommunication & Computer Engineering, Korea Aerospace University) ;
  • Lee, Seongjoo (Department of Information and Communication Engineering, Sejong University) ;
  • Kim, Jaeseok (School of Electrical and Electronic Engineering, Yonsei University)
  • 투고 : 2013.07.26
  • 발행 : 2013.11.25
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초록

본 논문은 전 병렬구조를 기반으로 고속으로 동작하며 다중 모드를 지원하는 quasi-cyclic (QC) low-density parity-check(LDPC) 복호기를 제안한다. 제안하는 QC-LDPC 복호기는 고속 throughput을 지원하기 위하여 전 병렬구조를 기반으로 설계되었다. 전 병렬구조를 사용함에 따라 발생하는 인터커넥션의 복잡도 문제는 broadcasting 기반의 sum-product 알고리즘의 사용과 저복잡도 순환 쉬프트 네트워크를 제안함으로써 해결하였다. 또한, 전 병렬구조에서 체크 노드 프로세서와 변수 노드 프로세서의 사용량이 많아 발생하는 복잡도 문제를 제안하는 결합된 체크 및 변수 노드 프로세서를 통하여 해결하였다. 제안하는 QC-LDPC 복호기는 라우팅 방식의 인터커넥션 네트워크, 다중 모드를 지원하는 결합된 체크 및 변수 노드 프로세서와 순환 쉬프트 네트워크를 통하여 다중 모드를 지원할 수 있다. 제안하는 QC-LDPC decoder는 100 MHz 클락 주파수로 동작하며, 다중 모드를 지원하고 (1944, 1620) QC-LDPC 부호에 대해서 8.1 Gbps의 throughput을 지원한다.

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

키워드

참고문헌

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