JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 256-Radix Crossbar Switch Using Mux-Matrix-Mux Folded-Clos Topology

  • Lee, Sung-Joon (Department of Electrical and Computer Engineering and Interuniversity Semiconductor Research Center at Seoul National University) ;
  • Kim, Jaeha (Department of Electrical and Computer Engineering and Interuniversity Semiconductor Research Center at Seoul National University)
  • Received : 2014.05.12
  • Accepted : 2014.11.04
  • Published : 2014.12.30
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Abstract

This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.

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References

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