IEMEK Journal of Embedded Systems and Applications (대한임베디드공학회논문지)

Institute of Embedded Engineering of Korea (대한임베디드공학회)
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Implementing IEEE1588 based Clock Synchronization for Networked Embedded System

네트워크 기반 임베디드 시스템을 위한 IEEE1588 시간동기 구현

  • Received : 2013.09.02
  • Accepted : 2013.11.30
  • Published : 2014.02.28
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Abstract

This paper presents a IEEE1588 based clock synchronization technique for a sRIO (Serial RapidIO) network which is applied to a submarine system. Clock synchronization plays a key role in the success of a networked embedded system. Recently, the IEEE1588 algorithm making use of dedicated chipset has been widely used for the synchronization of various industrial applications. However, there is no chipset available for the sRIO network that can offer many advantages, such as low latency and jitter. In this paper, the IEEE1588 algorithm for a sRIO network is implemented using only software without any dedicated chipset. The proposed approach is verified with experimental setup.

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References

  1. G. Pottie, W. Kaiser, "Principles of embedded networked system design," Cambridge university press, pp.1-3, 2005.
  2. K. Tanaka, Embedded systems - high performance systems, applications and projects, InTech, Chapters Published, 2012.
  3. H. Zeng, J. Guo, Z. Xiao, "Real-time embedded maintenance system of hydrogenerator excitation system," Proceedings of the International Conference on Condition Monitoring and Diagnosis, pp.402-406, 2008.
  4. D. Bouvier, "RapidIO: the interconnect architecture for high performance embedded systems," RapidIO Trade Association, pp.1-3, 2003.
  5. G. Shippen, "System interconnect fabrics: ethernet versus RapidIO technology," RapidIO Trade Association, 2007.
  6. B. Li, X. Ma, S. Yan, L. Yang, "A sonar array processing system based on multicore DSPs," Proceedings of the IEEE International Conference on Signal Processing, Vol. 1, pp.421-424, 2012.
  7. F. Zhang, Q. Wu, G. Ren, "A high-speed serial transport platform based on SRIO for high-resolution image," Proceedings of International Congress on Image and Signal Processing, Vol. 5, pp.2441-2444, 2010.
  8. A. Klilou, S. Belkouch, P. Elleaume, P. LeGall, F. Bourzeix, M.M. Hassani, "Performance optimization of high-speed Interconnect Serial RapidIO for onboard processing," Proceedings of the International Conference on Complex System, pp.1-6, 2012.
  9. M. Schmid, F. Hannig, J. Teich, "Power management strategies for Serial RapidIO endpoints in FPGAs," Proceedings of the IEEE Annual International Symposium on Field Programmable Custom Computing Machines, pp.101-108, 2012.
  10. F. Wu, S. Jia, Y. Wang, "A serial physical layer design in RapidIO," Proceedings of the IEEE International Conference on Electron Devices and Solid-State Circuits, pp.1-4, 2010.
  11. L. Lamport, "Time, clocks, and the ordering of events in a distributed system," Communication of the ACM, Vol. 21, No. 7, pp.558-565, 1978. https://doi.org/10.1145/359545.359563
  12. H. Kopetz, Real-time systems: design principles for distributed embedded application, Springer, pp.51-68, 2011.
  13. A. Mohammad, M. Behnam, "Implementing a clock synchronization protocol on a multi-master switched ethernet network," Proceedings of the IEEE Conference on Emerging Technologies & Factory Automation, pp.1-10, 2013.
  14. A. Mahmood, R. Exel, "Servo design for improved performance in software time stamping-assisted WLAN synchronization using IEEE 1588," Proceedings of the IEEE Conference on Emerging Technologies & Factory Automation, pp.1-8, 2013.
  15. NTP, "Network time protocol (Version3) specification, implementation and analysis," University of Delaware, Network Working Group, pp.8-33, 1992.
  16. K. Lee, J. Eidson, "IEEE standard for a precision clock synchronization protocol for networked measurement and control system," IEEE Instrumentation and Measurement Society, pp.1-40, 2008.
  17. M. Anyaegbu, C. Wang, W. Berrie, "Dealing with packet delay variation in IEEE 1588 synchronization using a sample-mode filter," IEEE Intelligent Transportation System Magazine, Vol. 5, No. 4, pp.20-27, 2013. https://doi.org/10.1109/MITS.2013.2267546
  18. G. Giorgi, C. Narduzzi, "Performance analysis of Kalman-filter-based clock synchronization in IEEE 1588 networks," IEEE Transaction on Instrumentation and Measurement, Vol. 60, No. 8, pp.2902-2909, 2011. https://doi.org/10.1109/TIM.2011.2113120
  19. J.H. Han, D.K. Jeong, "A practical implementation of IEEE 1588-2008 transparent clock for distributed measurement and control system," IEEE Transaction on Instrumentation and Measurement, Vol. 59, No. 2, pp.433-439, 2010. https://doi.org/10.1109/TIM.2009.2024371
  20. Z. Du, Y. Lu, Y. Ji, "An enhanced end-to-end transparent clock mechanism with a fixed delay ratio," IEEE Communications Letters, Vol. 15, No. 8, pp.872-874, 2011. https://doi.org/10.1109/LCOMM.2011.062911.110918
  21. A. Bondavalli, F. Brancati, A. Flammini, S. Rinaldi, "Master failure detection protocol in internal synchronization environment," IEEE Transactions on Instrumentation and Measurement, Vol. 62, No. 1, pp.4-12, 2013. https://doi.org/10.1109/TIM.2012.2209916
  22. G. Gaderer, P. Loschmidt, T. Sauter, "Improving fault tolerance in high-precision clock synchronization," IEEE Transaction on Industrial Informatics, Vol. 6, No. 2, pp.206-215, 2010. https://doi.org/10.1109/TII.2010.2044580
  23. S. Lv, Y. Lu, Y. Ji, "An enhanced IEEE 1588 time synchronization for asymmetric communication link in packet transport network," IEEE Communications Letters, Vol. 14, No. 8, pp.764-766, 2010. https://doi.org/10.1109/LCOMM.2010.08.091601
  24. S.W. Lee, S.G. Lee, C.S. Hong, "An accuracy enhanced IEEE 1588 synchronization protocol for dynamically changing and asymmetric wireless links," IEEE Communication Letters, Vol. 16, No. 2, pp.190-192, 2012. https://doi.org/10.1109/LCOMM.2011.092011.110582
  25. S. Fuller, "RapidIO: the embedded system interconnect," John Wiley & Sons Ltd, Rapidio Trade Association, pp.13-26, 2005.
  26. Texas Instruments, "KeyStone architecture serial rapidIO (SRIO) user guide," Texas Instruments, pp.1-8, 2011.
  27. A. V. Schedl, "Design and simulation of clock synchronization in distributed systems," PhD Thesis, Technical University of Vienna, Austria, 1996.