한국인터넷방송통신학회논문지 (The Journal of the Institute of Internet, Broadcasting and Communication)

  • 제14권3호
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  • Pages.163-169
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  • 2014
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  • 2289-0238(pISSN)
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  • 2289-0246(eISSN)
한국인터넷방송통신학회 (The Institute of Internet, Broadcasting and Communication)
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비대칭적 멀티코어 프로세서의 성능 연구

Performance Study of Asymmetric Multicore Processor Architectures

  • 이종복 (한성대학교 정보통신공학과)
  • 투고 : 2014.04.30
  • 심사 : 2014.06.13
  • 발행 : 2014.06.30
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⟨ 이전 논문 다음 논문 ⟩

초록

현재 범용 컴퓨터 시스템을 구축할 때 성능을 높이기 위하여 멀티코어 프로세서가 널리 이용되고 있으며, 멀티코어 프로세서의 구조는 크게 대칭적 구조와 비대칭적 구조로 나뉜다. 비대칭적 멀티코어 프로세서는 크고 복잡한 고성능의 코어와, 작고 간단한 저성능의 프로세서들로 구성되며, 대칭적 멀티코어 프로세서에 비하여 더욱 성능과 효율이 높은 것으로 알려져 있다. 본 논문에서는 다양한 구성을 갖는 비대칭적 쿼드코어 및 옥타코어 프로세서에 대하여 SPEC 2000 벤치마크를 통하여 모의실험을 수행하여 그 성능을 측정하고, 대칭적 쿼드코어 및 옥타코어 프로세서와 그 성능을 비교하였다.

Recently, the importance of multicore processor system is growing rapidly. Multicore processors are classified either as symmetric or asymmetric. Asymmetric multicore processors consist of a high performance complex core and number of low performance simple cores, and are known to be more efficient than symmetric multicore processors. Therefore, performance impact on various configurations of asymmetric multi-core processor needs to be studied. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for different asymmetric quad-core and octa-core processors and compared to the corresponding symmetric ones.

키워드

참고문헌

  1. J. B. Lee, "A Study of Trace-driven Simulation for Multicore Processor Architectures," The Journal of The Institute of Internet, Broadcasting and Communication(JIIBC), Vol. 12, No. 3, pp. 9-13, Jun. 2012.
  2. J. B. Lee, "Performance Anaylsis of Multicore Processor Architectures Based On Cache Size Effects," The Journal of The Institute of Internet, Broadcasting and Communication(JIIBC), Vol. 12, No. 6, pp. 175-180, Dec. 2012.
  3. J. B. Lee, "Performance Study of Multi-core In-Order Superscalar Processor Architectures," The Journal of The Institute of Internet, Broadcasting and Communication(JIIBC), Vol. 12, No. 5, pp. 123-128, Oct. 2012.
  4. J. B. Lee, "A Performance Study of Embedded Multicore Processor Architectures," The Journal of The Institute of Internet, Broadcasting and Communication(JIIBC), Vol. 13, No. 1, pp. 163-169, Feb. 2013. https://doi.org/10.7236/JIIBC.2013.13.1.163
  5. J. B. Lee, "Performance Study of Multicore Digital Signal Processor Architectures ," The Journal of The Institute of Internet, Broadcasting and Communication(JIIBC), Vol. 13, No. 14, pp. 171-177, Aug. 2013. https://doi.org/10.7236/JIIBC.2013.13.4.171
  6. R. Kumar et al, "Single-ISA heterogeneous Multicore Architectures for Heterogeneous for Multithreaded Workload Performance," Annual International Symposium on Computer Architecture, Mar. 2004.
  7. Hourd, Jon, et al. "Exploring Practical Benefits of Asymmetric Multicore Processors." Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures, Apr. 2009.
  8. T. Ungerer, B. Robic, and J. Silk, "Multithreaded Processors," The Computer Journal, Vol. 45, No. 3, 2002
  9. G. S. Sohi, S. E. Breach, and T. N. Vijaykumar, "Multiscalar Processors," Proceedings of the 22nd annual international symposium on Computer architecture, pp. 414-425, May 1995.
  10. T-Y. Yeh and Y. N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," in Proceedings of the 19th International Symposium on Computer Architecture, pp.124-134, May. 1992.
  11. A. Rico, A. Duran. F. Cabarcas, Y. Etsion, A. Ramirex, and M. Valero, "Trace-driven Simulation of Multithreaded Applications," ISPASS, 2011.
  12. T. Austin, E. Larson, and D. Ernest, "SimpleScalar : An Infrastructure for Computer System Modeling," Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002. https://doi.org/10.1109/2.982917

피인용 문헌

  1. Development of Vehicle LDW Application Service using AUTOSAR Platform on Multi-Core MCU vol.14, pp.4, 2014, https://doi.org/10.7236/JIIBC.2014.14.4.113