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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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CMOS-Memristor Hybrid 4-bit Multiplier Circuit for Energy-Efficient Computing

  • Vo, Huan Minh (Dept. of Electrical and Electronics Engineering, the University of Technical Education) ;
  • Truong, Son Ngoc (Dept. of Electronics Engineering, Kookmin University) ;
  • Shin, Sanghak (Dept. of Electronics Engineering, Kookmin University) ;
  • Min, Kyeong-Sik (Dept. of Electronics Engineering, Kookmin University)
  • Received : 2013.12.26
  • Accepted : 2014.06.10
  • Published : 2014.06.30
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Abstract

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

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References

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