Journal of electromagnetic engineering and science

The Korean Institute of Electromagnetic Engineering and Science (한국전자파학회)
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A CMOS Stacked-FET Power Amplifier Using PMOS Linearizer with Improved AM-PM

  • Kim, Unha (School of Electrical Engineering and Computer Science and INMC, Seoul National University) ;
  • Woo, Jung-Lin (School of Electrical Engineering and Computer Science and INMC, Seoul National University) ;
  • Park, Sunghwan (School of Electrical Engineering and Computer Science and INMC, Seoul National University) ;
  • Kwon, Youngwoo (School of Electrical Engineering and Computer Science and INMC, Seoul National University)
  • Received : 2014.03.18
  • Accepted : 2014.04.30
  • Published : 2014.06.30
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Abstract

A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a $0.18-{\mu}m$ silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance ($C_{gs}$) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improved AM-PM. The linearizer is used at the gate of the driver-stage instead of main-stage transistor, thereby avoiding excessive capacitance loading while compensating the AM-PM distortions of both stages. The fabricated 836.5 MHz linear PA module shows an adjacent channel leakage ratio better than -40 dBc up to the rated linear output power of 27.1 dBm, and power-added efficiency of 45.6% at 27.1 dBm without digital pre-distortion.

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References

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