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Mixed Dual-rail Data Encoding Method Proposal and Verification for Low Power Asynchronous System Design

저전력 비동기식 시스템 설계를 위한 혼합형 dual-rail data encoding 방식 제안 및 검증

  • Chi, Huajun (Department of Electronics and Electrical Engineering, Pusan National University) ;
  • Kim, Sangman (Department of Electronics and Electrical Engineering, Pusan National University) ;
  • Park, Jusung (Department of Electronics and Electrical Engineering, Pusan National University)
  • 지화준 (부산대학교 전자전기공학과) ;
  • 김상만 (부산대학교 전자전기공학과) ;
  • 박주성 (부산대학교 전자전기공학과)
  • Received : 2014.02.21
  • Accepted : 2014.06.27
  • Published : 2014.07.25

Abstract

In this paper, we proposed new dual-rail data encoding that mixed 4-phase handshaking protocol and 2-phase handshaking protocol for asynchronous system design to reduce signal activities and power consumption. The dual-rail data encoding 4-phase handshaking protocol should leat to much signal activities and power consumption by return to space state. Ideally, the dual-rail data encoding 2-phase handshaking protocol should lead to faster circuits and lower power consumption than the dual-rail 4-phase handshaking protocol, but can not designed using standard library. We use a benchmark circuit that contains a multiplier block, an adder block, and latches to evaluate the proposed dual-rail data encoding. The benchmark circuit using the proposed dual-rail data encoding shows an over 35% reduction in power consumption with 4-phase dual-rail data encoding.

References

  1. I. Sutherland and S. Fairbanks, "Gasp; a Minimal FIFO Control," Proc. Int'l Symp. Advanced Research in Asynchronous Circuits and Systems, pp.46-53, 2001.
  2. M. Singh and S.M. Nowick, "MOUSETRAP: High-speed Transition-signaling Asynchronous Pipelines," IEEE Trans. on VLSI Systems,Vol.15, No.6, pp.684-698, June 2007. https://doi.org/10.1109/TVLSI.2007.898732
  3. J. Pangjun and S.S. Sapatnekar, "Low-power Clock Distribution Using Multiple Voltages and Reduced Swings," IEEE Trans. on VLSI Systems, Vol.10, No.2, pp.309-318, June 2002. https://doi.org/10.1109/TVLSI.2002.1043334
  4. J. Sparso and S. Furber, "Principles of Asynchronous Circuit Design: a System Perspective,"Kluwer Academic Publishers, 2001.
  5. Richard F. Tinder, "Asynchronous Sequential Circuit Design and Analysis", Morgan & Claypool Publishers, 2008.
  6. Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti, "A Designer's Guide to Asynchronous VLSI", Cambridge University Press, 2010.
  7. Sung-Nam Kim, Myeong-Hoon Oh, Chi-Hoon Shin, Youngwoo Kim, Seongwooon Kim, "The Trend and Prospect of Asynchronous Design Technology", IEIE conference, pp.1754-1750, 2011.
  8. Sanghoon Kwak, Hyung-Woo Lee, Gyudong Choi, Myeng-hoon Oh, Sungnam Kim, Sungwoon Kim, Dongsoo Har, "Synthesis of Area-Efficient Delay-Insensitive Asynchronous Circuit Using BALSA", IEIE conference pp.989-990, 2008.

Cited by

  1. Design of Low Power and High Speed NCL Gates vol.52, pp.2, 2015, https://doi.org/10.5573/ieie.2015.52.2.112