References
- K. Oh, J. Ma, S. Kim and S. E. Kim, "Interconnect Process Technology for High Power Delivery and Distribution", J. Microelectron. Packag. Soc., 19(3), 9 (2012).
- N. H. Khan, S. M. Alam and S. Hassoun, "Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies", IEEE Trans. VLSI systems, 19(4), 647 (2011). https://doi.org/10.1109/TVLSI.2009.2038165
- R. Plieninger, M. Dittes and K. Pressel, "Modern IC packaging trends and their reliability implications", Microelectron. Reliab., 46(9), 1868 (2006). https://doi.org/10.1016/j.microrel.2006.08.008
- K. Oh, J. S. Ma, S. Kim and S. E. Kim, "Fabrication of Advanced Bump Layer for IC Power Delivery", J. Nanosci. Nanotech., 13, 6447 (2013). https://doi.org/10.1166/jnn.2013.7626
- M. Ketkar and E. Chiprout, "A microarchitecture based framework for pre- and post-silicon power delivery analysis", Microarchitecture, 42, 179 (2009).
- N. H. Khan, S. M. Alam and S. Hassoun, "System level comparison of power delivery design for 2D and 3D ICs 3D System Integration", IEEE 3DIC, Osaka, Japan, Sep. 28, 1 (2009).
- M. Budnik and K. Roy, "A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies", IEEE Trans. VLSI Systems, 14(12), 1336 (2006). https://doi.org/10.1109/TVLSI.2006.887810
- G. Schrom, P. Hazucha, J. Hahn, V. Kursun, D. Gardner, S. Narendra, T. Karnik and V. De, "Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90 nm Technology Generation", ISLPED, Newport, US, Aug. 9, 263 (2004).
- I. Song, M. Lee, S. Kim and S. E. Kim, "Development of Cu CMP Process for Cu-to-Cu Wafer Stacking", J. Microelectron. Packag. Soc., 20(4), 81 (2013). https://doi.org/10.6117/kmeps.2013.20.4.081
- E. Malysha, U. Landau and S. Chivilikhin, "Modeling the deposit thickness distribution in Cu electroplating of semiconductor wafer interconnects", Proc. of the AIChE, Nov. 16, San Francisco, US (2003).
- S. Kang, J. Lee, E. Kim, N. Lim, S. Kim, S. Kim and S. E. Kim, "Fabrication and Challenges of Cu-to-Cu Wafer Bonding", J. Microelectron. & Packag. Soc., 19(2), 29 (2012). https://doi.org/10.6117/kmeps.2012.19.2.029
- R. Stengl, T. Tan and U. Gsele, "A model for the silicon wafer bonding process", Jpn. J. Appl. Phys., 28(1), 1735 (1989). https://doi.org/10.1143/JJAP.28.1735
- P. Gueguen, L. Di Cioccio, P. Gergaud, M. Rivoire, D. Scevola, M. Zussy, A. Charvera, L. Ballya, D. Lafonda and L. Clavelier, "Copper direct bonding characterization and its interests for 3D integration", J. Electrochem. Soc., 156(10), H772 (2009). https://doi.org/10.1149/1.3187271
- E. Kim, M. Lee, S. Kim and S. E. Kim, "Ti/Cu CMP Process for Wafer Level 3D Integration", J. Microelectron. Packag. Soc., 19(3), 37 (2012). https://doi.org/10.6117/kmeps.2012.19.3.037