Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
권호 표지
DOI QR코드

DOI QR Code

The Effects of Cu TSV on the Thermal Conduction in 3D Stacked IC

3차원 적층 집적회로에서 구리 TSV가 열전달에 미치는 영향

  • Ma, Junsung (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology) ;
  • Kim, Sarah Eunkyung (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology) ;
  • Kim, Sungdong (Dept. of Mechanical System Design Eng., Seoul National University of Science and Technology)
  • 마준성 (서울과학기술대학교 NID 융합기술대학원) ;
  • 김사라은경 (서울과학기술대학교 NID 융합기술대학원) ;
  • 김성동 (서울과학기술대학교 기계시스템디자인공학과)
  • Received : 2014.09.19
  • Accepted : 2014.09.29
  • Published : 2014.09.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this study, we investigated the effects of Cu TSV on the thermal management of 3D stacked IC. Combination of backside point-heating and IR microscopic measurement of the front-side temperature showed evolution of hot spots in thin Si wafers, implying 3D stacked IC is vulnerable to thermal interference between stacked layers. Cu TSV was found to be an effective heat path, resulting in larger high temperature area in TSV wafer than bare Si wafer, and could be used as an efficient thermal via in the thermal management of 3D stacked IC.

본 연구에서는 3차원 적층 집적회로 구조에서 Cu TSV를 활용한 열관리 가능성에 대해 살펴보았다. Cu TSV가 있는 실리콘 웨이퍼와 일반 실리콘 웨이퍼 후면부를 점열원을 이용하여 가열한 후 전면부의 온도 변화를 적외선 현미경을 이용하여 관찰하였다. 일반 실리콘 웨이퍼의 경우 두께가 얇아지면서 국부적인 고온영역이 관찰됨으로서 적층 구조에서 층간 열문제의 가능성을 확인할 수 있었다. TSV 웨이퍼의 경우 일반 실리콘 웨이퍼보다 넓은 영역의 고온 분포를 나타내었으며, 이는 Cu TSV를 통한 우선적인 열전달로 인한 것으로 적층 구조에서 Cu TSV를 이용한 효과적인 열관리의 가능성을 나타낸다.

Keywords

References

  1. J. H. Lau and G. Tang, "Thermal Management of 3D IC Integration with TSV(Through Silicon Via)", IEEE Proceedings of ECTC, San Diego, 635 (2009).
  2. A. J. McNamara, Y. Joshi and Z. M. Zhang, "Characterization of Nanostructured Thermal Interface Materials: A Review", Int. J. Therm. Sci., 62, 2 (2011).
  3. Jun Xu and T. S. Fisher, "Enhancement of Thermal Interface Materials with Carbon Nanotube Arrays", Int. J. Heat Mass Transfer, 49(9-10), 1658 (2006). https://doi.org/10.1016/j.ijheatmasstransfer.2005.09.039
  4. M. Park, S. Kim and S. E. Kim, "TSV Liquid Cooling System for 3D Integrated Circuits", J. Microelectron. Packag. Soc., 20(3), 1 (2013).
  5. J. Darabi and K. Ekula, "Development of a Chip-Integrated Micro Cooling Device", Microelectron. J., 34(11), 1067 (2003). https://doi.org/10.1016/j.mejo.2003.09.010
  6. B. Sung, "Thermal enhancement of stacked dies using thermal vias", Master thesis, the university of Texas Arlington, (2006).
  7. J. Cong and Y. Zhang. "Thermal via planning for 3-D ICs." IEEE/ACM International Conference on Computer-Aided Design, 745 (2005).
  8. B. K. Yu, M. Y. Kim and T. S. Oh, "Anisotropic Wet-Etching Process of Si Substrate for Formation of Thermal Vias in High-Power LED Packages", J. Microelectron. Packag. Soc., 19(4), 51 (2012). https://doi.org/10.6117/kmeps.2012.19.4.051
  9. H. D. Young, "University Physics", 7th Ed., Table 15-5, Addison Wesley, (1992).