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A Study on the Full-HD HEVC Encoder IP Design

고해상도 비디오 인코더 IP 설계에 대한 연구

  • Lee, Sukho (SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Cho, Seunghyun (SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Kim, Hyunmi (SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Lee, Jehyun (School of Electrical and Communication Engineering, Dongyang Mirae University)
  • 이석호 (한국전자통신연구원 시스템반도체연구부) ;
  • 조승현 (한국전자통신연구원 시스템반도체연구부) ;
  • 김현미 (한국전자통신연구원 시스템반도체연구부) ;
  • 이제현 (동양미래대학교 전기전자통신공학부)
  • Received : 2015.09.16
  • Accepted : 2015.11.18
  • Published : 2015.12.25

Abstract

This paper presents a study on the Full-HD HEVC(High Efficiency Video Coding) encoder IP(Intellectual Property) design. The designed IP is for HEVC main profile 4.1, and performs encoding with a speed of 60 fps of full high definition. Before hardware and software design, overall reference model was developed with C language, and we proposed a parallel processing architecture for low-power consumption. And also we coded firmware and driver programs relating IP. The platform for verification of developed IP was developed, and we verified function and performance for various pictures under several encoding conditions by implementing designed IP to FPGA board. Compared to HM-13.0, about 35% decrease in bit-rate under same PSNR was achieved, and about 25% decrease in power consumption under low-power mode was performed.

본 논문에서는 고해상도(Full-HD)급의 비디오를 처리할 수 있는 고효율 비디오 코딩(HEVC) 표준을 따르는 인코더 IP 설계에 대하여 기술한다. 설계된 IP는 HEVC 메인 프로파일 4.1급에 해당되며, 프레임 레이트는 60 fps 로 실시간 인코딩 가능하다. 하드웨어 및 소프트웨어 IP 설계 전에 C 언어로 전체 참조 모델을 개발하였으며 고속처리를 위한 병렬처리구조와 저 전력을 위한 스킵모드를 제안하였다. 또한 IP 관련 펌웨어 및 드라이버 프로그램을 작성하였다. IP 검증을 위한 플랫폼을 개발하였고 설계된 통합 IP를 FPGA 보드로 구현하여 다양한 영상에 대하여 여러 인코딩 조건에서 기능 및 성능을 검증하였다. HM-13.0대비 동일 PSNR에서 약 35% 정도의 비트율 감소와 저전력 모드에서 약 25% 정도의 전력 소모 감소 효과가 있었다.

Keywords

References

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