Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
권호 표지
DOI QR코드

DOI QR Code

Warpage Analysis for Top and Bottom Packages of Package-on-Package Processed with Thin Substrates

박형 기판을 사용한 Package-on-Package용 상부 패키지와 하부 패키지의 Warpage 분석

  • Park, D.H. (Department of Materials Science and Engineering, Hongik University) ;
  • Shin, S.J. (Department of Materials Science and Engineering, Hongik University) ;
  • Ahn, S.G. (Institute of Technology, Amkor Technology Korea) ;
  • Oh, T.S. (Department of Materials Science and Engineering, Hongik University)
  • 박동현 (홍익대학교 공과대학 신소재공학과) ;
  • 신수진 (홍익대학교 공과대학 신소재공학과) ;
  • 안석근 (앰코코리아 기술연구소) ;
  • 오태성 (홍익대학교 공과대학 신소재공학과)
  • Received : 2015.06.22
  • Accepted : 2015.06.26
  • Published : 2015.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

Warpage analysis has been performed for top and bottom packages of thin package-on-packages processed with different epoxy molding compounds (EMCs). Warpage deviation was measured for packages molded with the same EMCs and also the warpage deviations of top and bottom substrates themselves were characterized in order to identify the major factor causing the package warpage. For the top and bottom packages processed with thin substrates, the warpage deviation of the substrates was large, which made it difficult to figure out the effect of EMC properties on the package warpage. Top packages, where the molding area of $13mm{\times}13mm$ covered the most of the substrate area ($14mm{\times}14mm$), exhibited similar warpage behavior with changing the temperature. On the other hand, bottom packages, where the molding area was only $8mm{\times}8mm$, exhibited the complex warpage behavior due to simultaneous occurrence of (+) and (-) warpages on the same package. Accordingly, the bottom packages showed dissimilar temperature-warpage behavior even being processed with the same EMCs.

박형 package-on-package의 상부 패키지와 하부 패키지에 대하여 에폭시 몰딩 컴파운드(EMC)에 따른 warpage 특성을 분석하였다. 또한 동일한 EMC로 몰딩한 패키지들의 warpage 편차를 측정하고 박형 상부 기판과 하부 기판 자체의 warpage 편차를 측정함으로서, 박형 패키지에서 warpage 편차를 유발하는 원인을 분석하였다. 박형 기판을 사용한 상부 및 하부 패키지에서는 기판 자체의 큰 warpage 편차에 기인하여 EMC의 물성이 패키지의 warpage에 미치는 영향을 규명하는 것이 어려웠다. EMC의 몰딩 면적이 $13mm{\times}13mm$로 기판($14mm{\times}14mm$)의 대부분을 차지하는 상부 패키지에서는 온도에 따른 warpage의 변화 거동이 유사하였다. 반면에 EMC의 몰딩 면적이 $8mm{\times}8mm$인 하부 패키지의 경우에는 (+) warpage와 (-) warpage가 한 시편에 모두 존재하는 복합적인 warpage 거동에 기인하여 동일한 EMC로 몰딩한 패키지들에서도 상이한 온도-warpage 거동이 측정되었다.

Keywords

References

  1. J. L. Leila, "Numerical Analysis of Thermomechanical Reliability of Through Silicon Vias (TSVs) and Solder Interconnects in 3-dimensional Integrated Circuits", Microelectron. Eng., 87(2), 208 (2010). https://doi.org/10.1016/j.mee.2009.07.022
  2. D. H. Park, D. M. Jung, and T. S. Oh, "Warpage Characteristics Analysis for Top Packages of Thin Package-on-Packages with Progress of Their Process Steps", J. Microelectron. Packag. Soc., 21(2), 65 (2014). https://doi.org/10.6117/kmeps.2014.21.2.065
  3. N. Vijayaragavan, F. Carson, and A. Mistry, "Package on Package Warpage - Impact on Surface Mount Yields and Board Level Reliability", Proc. 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 389, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008).
  4. H. Eslampour, Y. C. Kim, S. W. Park, T., and W. Lee, "Low Cost Cu Column fcPoP Technology", Proc. 62nd Electronic Components and Technology Conference (ECTC), San Diego, 871, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2012).
  5. F. Roa, "Very Thin POP and SIP Packaging Approaches to Achieve Functionality Integration prior to TSV Implementation", Proc. 64th Electronic Components and Technology Conference (ECTC), Orlando, 1656, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2014).
  6. C. G. Kim, H. S. Choi, M. S. Kim, and T. S. Kim, "Packaging Substrate Bending Prediction due to Residual Stress", J. Microelectron. Packag. Soc., 20(1), 21 (2013). https://doi.org/10.6117/kmeps.2013.20.1.021
  7. J. Zhao, Y. Luo, Z. Huang, and R. Ma, "Effects of Package Design on Top PoP Package Warpage", Proc. 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1081, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008).
  8. C. H. Chien, Y. C. Chen, Y. T. Chio, T. Chen, C. C. Hsieh, J. J. Yan, W. Z Chen, and Y. D. Wua, "Influences of the Moisture Absorption on PBGA Package's Warpage during IR Reflow Process", Microelectron. Reliab., 43(1), 131 (2003). https://doi.org/10.1016/S0026-2714(02)00283-4
  9. G. Kelly, C. Lyden, W. Lawton, J. Barrett, A. Saboui, H. Pape, and H. Peters, "The Importance of Molding Compound Chemical Shrinkage in the Stress and Warpage Analysis of PQFPs", Proc. 45th Electronic Components and Technology Conference (ECTC), Las Vegas, 296, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (1996).
  10. M. J. Yim, R. Strode, R. Adimula, J. J. Zhang and C. Yoo, "Ultra Thin Top Package using Compression Mold: Its Warpage Control", Proc. 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1141, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2011).
  11. W. D. van Driel, G. Q. Zhang, J. H. J. Janssen, L. J. Ernst, F. Su, K. S. Chian, and S. Yi, "Prediction and verification of process-induced warpage of electronic packages", Microelectron. Reliab., 43(5), 765 (2003). https://doi.org/10.1016/S0026-2714(03)00057-X
  12. C. Chiu, K. C. Chang, J. Wang, C. H. Lee, K. Shen, and L. Wang, "Challenges of Thin Core Substrate Flip Chip Package on Advanced Si Nodes", Proc. 57th Electronic Components and Technology Conference (ECTC), Reno, 22, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2007).
  13. B. H. Lee, M. K. Kim, and J. W. Joo, "Thermo-Mechanical Behavior of WB-PBGA Packages with Pb-Sn Solder and Lead-Free Solder Using Moire Interferometry", J. Microelectron. Packag. Soc., 17(3), 17 (2010).
  14. JEDEC Standard JESD22-B112A, "Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature", JEDEC Solid State Technology Association, Arlington (2009).
  15. M. J. Yim, R. Strode, R. Adimula, and C. Yoo, "Effects of Material Properties on PoP Top Package Warpage Behaviors", Proc. 60th Electronic Components and Technology Conference (ECTC), Las Vegas, 1071, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2010).
  16. S. Michaelides and S. K. Sitaraman, "Die Cracking and Reliable Die Design for Flip-Chip Assemblies", IEEE Transactions on Advanced Packaging, 22(4), 602 (1999). https://doi.org/10.1109/6040.803452
  17. Y. Sawada, K. Harada, and H. Fujioka, "Study of Package Warpage Behavior for High-Performance Flip-Chip BGA", Microelectron. Reliab., 43(3), 465 (2003). https://doi.org/10.1016/S0026-2714(02)00294-9
  18. N. Boyard, A. Millischer, V. Sobotka, J. Bailleul, and D. Delaunay, "Behaviour of a Moulded Composite Part: Modelling of Dilatometric Curve (Constant Pressure) or Pressure (Constant Volume) with Temperature and Conversion Degree Gradients", Composite Sci. Technol., 67(6), 943 (2007). https://doi.org/10.1016/j.compscitech.2006.07.004
  19. S. Y. Yang, Y. Jeon, S. Lee, and K. Paik, "Solder Reflow Process Induced Residual Warpage Measurement and Its Influence on Reliability of Flip-Chip Electronic Packages", Microelectron. Reliab., 46(2), 512 (2006). https://doi.org/10.1016/j.microrel.2005.06.007
  20. S. H. Cho, T. E. Chang, J. Y. Lee, H. P. Park, Y. Ko, and G. Park, "New Dummy Design and Stiffener on Warpage Reduction in Ball Grid Array Printed Circuit Board", Microelectron. Reliab., 50(2), 242 (2010). https://doi.org/10.1016/j.microrel.2009.10.009

Cited by

  1. Reliability Characteristics of a Package-on-Package with Temperature/Humidity Test, Temperature Cycling Test, and High Temperature Storage Test vol.23, pp.3, 2016, https://doi.org/10.6117/kmeps.2016.23.3.043