A New Control Strategy for a Three-Phase PWM Current-Source Rectifier in the Stationary Frame

Abstract

This paper presents a novel power control strategy for PWM current-source rectifiers (CSRs) in the stationary frame based on the instantaneous power theory. In the proposed control strategy, a virtual resistance based on the capacitor voltage feedback is used to realize the active damping. In addition, the proportional resonant (PR) controller under the two-phase stationary coordinate is designed to track the ac reference current and to avoid the strong coupling brought about by the coordinate transformation. The limitations on improving steady-state performance of the PR controller is investigated and mitigated using a cascaded lead-lag compensator. In the z-domain, a straightforward procedure is developed to analyze and design the control-loop with the help of MATLAB/SISO software tools. In addition, robustness against parameter variations is analyzed. Finally, simulation and experimental results verify the proposed control scheme and design method.

I. INTRODUCTION

Although the three-phase pulse-width modulated (PWM) voltage-source rectifier (VSR) is widely used as the main topology for power electronic conversion, the current-source rectifier (CSR) has the following particular advantages [1]-[4]: 1) ability to tolerate phase leg shoot-through; 2) sinusoidal input current and adjustable power factor; 3) direct current control; 4) a wide output-voltage control range, etc. These features make the CSR an attractive solution in many industrial applications, such as active front-end rectifiers [5]; SMES [6]; battery chargers for EVs [7]; STATCOMs [8], etc. Furthermore, the recent advances in semiconductor devices and magnetic component technology may help to overcome the obvious fundamental disadvantage of conduction losses and dc series inductor losses [9].

Since the topologies of the CSR and VSR are functional duals, it can be expected that the advanced control strategies that have been developed for the VSR, such as direct power control [10], repetitive control [11], synchronous frame with decoupled proportional-integral (PI) control [12], and sliding-mode control [13], can be directly applied to the CSR to achieve a similar performance.

To suppress the pollution of a utility by high-frequency current harmonics, an inductor-capacitor (LC) filter is always required at the ac-side of the CSR. From a control perspective, the VSR is a first-order system, while the CSR is a second-order system. Hence, strategies used to set the controller gains for the VSR are not necessarily directly applicable to the CSR. Due to the LC filter, the CSR system has an inherent resonance problem, which will introduce transient distortions and steady-state harmonics around the LC resonant frequency or even affect the overall system stability [14]. A direct method to damp the LC resonance is to insert a resistor in series or in parallel with the filter. However, this solution results in additional power dissipation, especially in high-power applications. To overcome this drawback, many kinds of active damping control strategies have been reported in recent years [15]-[19]. Therefore, optimizing the gains of a system with this kind of additional feedback path is more complex than the optimization of a simple first-order VSR closed-loop regulator. As a result, it and needs additional investigation.

In recent literatures, several control strategies have been proposed for the three-phase CSR. Most of these stratagies use transformations to a rotational coordinate frame and PI controllers. In [20], a feed-forward signal compensation method using the LC filer model is presented to damp supply current oscillations. Nevertheless, only a dc current controller is used to produce the modulation signal resulting in non-accurate active and reactive power control. In [21], the authors use capacitor-voltage feedback to mitigate the resonance in the three-phase CSR. Meanwhile, the derivative feedback control of the inductor current is adopted to damp the input filter resonance in [22]. However, like [20], these control structures are based on dc current control in one stage without inner ac current controllers. In order to maintain control-loop stability, it is beneficial for the controller to have information on as many control variables as possible. In [23], the paper employs cascaded controllers with an outer dc current controller and an inner grid-side ac current controller. However, it does do not consider the coupling effect or the mitigation of the input LC filter resonance. All of the aforementioned control schemes use synchronous rotating frame PI controllers to obtain a zero steady-state error. Therefore, they are limited by a significant computational burden arising from the need for coordinate transformations and phase detection of the input voltages.

Recently, proportional-resonant (PR) controllers have been shown to be a good choice in current control loops [24]-[26]. With this method, the rotational transformation and PLL strategy are both avoided in the two-phase stationary frame, and the PR controllers are capable of tracking ac signals with a zero steady-state error. As a result, the control process can be simplified. However, the PR controller is one multi-order system. Thus, it is rather difficult to design the controller parameters and keep the control system stable. In [19], a PR regulator design method that combines the design rules of the technical optimum (TO) and the symmetrical optimum (SO) is proposed. However, this empirical formula design method is more sensitive to variations of the circuit parameters, which affects the system stability and dynamic response.

This paper is structured as follows. In Section II, the averaged switch model of the three-phase CSR in the stationary frame is derived by analyzing the working principle and operational conditions. Then, in Section III, a voltage-oriented power control strategy based on the instantaneous power theory is proposed. To reduce grid-side current distortion or even system instability, an active damping method with capacitor-voltage feedback is embedded into the control loop to weaken the LC resonance. Based on inner-current loop Bode diagrams, deep insights into the limitations on the dynamic performance of PR controllers are provided in Section IV. In this section, a new cascaded lead-lag compensation method is presented, which makes the inner loop equivalent to a simple first-order system. A zero-pole placement technique can be utilized to design the inner and outer loop gains. Finally, simulation and experimental results are presented in Section V and VI to verify the feasibility and effectiveness of the proposed control strategy.

 

II. AVERAGED MODEL OF THE THREE-PHASE CSR

The topology of a three-phase grid-connected CSR is shown in Fig. 1. The switching element Sx (x=1, 2,…, 6) consists of an insulated gate bipolar transistor (IGBT) and an ultrafast recovery diode in series, which results in the reverse voltage blocking capability. An LC filter is required at the input side of the three-phase CSR to filter out the switching frequency harmonic components and to assist in the switching devices commutation. At the dc-link, the inductor Ldc is employed to smooth the load current. To reduce the devices conduction losses and control logic, an additional freewheeling diode Dw is connected in parallel on the dc-link.

Fig. 1.Schematic diagram of the three-phase PWM CSR.

Based on the system in Fig. 1, the mathematical model of the CSR in the a-b-c reference frame is described as:

Where idc stands for the dc-link current; [iabc]=[ia ib ic]T, [eabc]=[ea eb ec]T, [vabc]=[va vb vc]T, and [mabc]=[ma mb mc]T denote the grid-side currents, the grid-side voltages, the voltages across the input filter capacitors, and the modulating signals of the CSR, respectively. L, C and Rg represent the filter inductance, the filter capacitor and its equivalent series resistance for each phase.

For a three-wire three-phase grid-connected converter, there is no zero-sequence injected grid current. Meanwhile, in order to simplify the analysis, suppose the three-phase voltage works in the balanced state. The transformation matrix from the a-b-c frame to the α-β frame is as follows:

Thus, the mathematical model in the stationary α-β reference frame can be expressed as:

Where [iαβ]=[iα iβ]T, [eαβ]=[eα eβ]T, [vαβ]=[vα vβ]T, and [mαβ]=[mα mβ]T .

According to (5)-(7), the s-domain average model of the CSR in the stationary α-β frame is shown in Fig. 2. Obviously, there is no rotating transformation and no coupling relationship.

Fig. 2.Average model of CSR in the Laplace domain.

 

III. PROPOSED CONTROL STRATEGY

A. PR Control Based on the Instantaneous Power Theory

By applying the p-q theory [27], the inputs instantaneous active p and reactive q powers of the CSR can be defined in the stationary α-β frame as:

Set the reference values of the instantaneous active and reactive powers as p* and q*, respectively. Then, the reference grid-side currents can be expressed as:

In general, three-phase PWM rectifiers should operate at a unity power factor. Therefore, the reactive power q* is controlled to be zero (q*=0), and the expressions of (9) can be simplified as:

According to the power balance principle, the dc-link active power is equal to the grid-side instantaneous active power, namely:

By considering the small-signal perturbations around the steady-state operating points equation (11) can be written as:

Since by definition îdc is a small-signal perturbation, îdc/<<1, the transfer function from the dc-link current to the grid-side instantaneous active power in the s-domain can be obtained as:

From (13), the systematic instantaneous active power can be controlled by adjusting the reference dc-link current . Then, the reference currents will be obtained to achieve input current control of the inner loop. At the same time, Gpd(s) is a first-order plant to maintain dc-link current in the reference value. Thus, a proportional integral (PI) controller is used in the outer current loop, with the transfer function shown below:

According to the aforementioned analysis, the overall control diagram of the proposed P-Q control, based on the stationary α-β frame, is illustrated in Fig. 3. There are three feedback control loops in this system: 1) two inner current loops that control the grid-side currents iα and iβ; and 2) one outer dc current feedback loop that controls the dc-link current idc. Assuming that the losses in the filter and rectifier are ignored, the instantaneous active power reference p∗ is generated by the dc-link current PI regulator, and the instantaneous reactive power reference q∗ is directly set to zero. Under the steady state, the α-β axis current references can then be obtained from (10). Unfortunately, for the ac reference, e.g., the current control in a three-phase converter in the stationary frame, applying conventional PI controllers lead to steady-state errors due to the finite gain at the fundamental frequency [28]. To track the reference current precisely, a proportional resonant (PR) controller is adopted as the controller of the inner current loop.

Fig. 3.Block diagram of the CSR system and its controls based on the stationary α-β frame.

B. Active Damping Control

The basic CSR input filter transfer function can be expressed as:

Thus, the resonance frequency ωn and the damping ratio ζ of the system can be readily derived as:

Due to the fact that the series resistance Rg of the filter inductor is so small, the system will suffer from a severe resonance problem. In order to reduce the resonant effect of the CSR system, an additional physical resistor can be inserted in series or parallel with the LC filter circuit, as shown in Fig. 4. This passive damping method is simple and reliable. However, these additional resistors result in energy losses, especially in high power applications. To overcome this drawback, several active damping methods have been proposed in recent years. Among them, the capacitor-voltage feedback (CVF) active damping method is applied in this paper due to its effectiveness and simple implementation [17]-[19]. Since the feedback loop of the capacitor-voltage active damping is incorporated into the system, the new input filter transfer function can be obtained as:

Fig. 4.Four possible locations of damping resistor.

According to (17), its resonance frequency and the damping ratio with the CVF are changeable, then:

It can be observed from (18) that the damping ratio ζ∗ can be easily adjusted by changing the feedback gain Kv. A Bode diagram of is plotted in Fig. 5. It shows that when the feedback gain increases from 0 to 0.4, the LC resonant peak is gradually damped. A bigger feedback gain is expected to provide a better damping effect. However, when Kv is too large, the rectifier system may become unstable. Furthermore:

Fig. 5.Bode diagram of the filter transfer function Gplant(s).

the selection of Kv is constrained by the dc-link current and modulation index [22]. Ultimately, according to Fig. 5, Kv=0.2 is chosen for the CVF active damping method.

 

IV. CONTROLLER DESIGN

A. Proposed Multi-Loop Controller

The general form of a PR controller is given by:

Which gives an infinite gain at a frequency of ω0 and a 180° phase shift. However, the PR controller defined by (19) can be challenging to physically realize. This is especially true when using a digital control system. Therefore, the quasi-PR controller in (20) is employed in the control scheme to avoid instability.

Where Krp is the proportional gain; Kr is the resonant controller gain; ω0 is set as the line frequency, ω0=2π·50; and ωc is the cutoff frequency, which determines the width of the resonant peak.

According to the previous analysis, the control model of the inner current loop for each phase can be shown in Fig. 6. When the feed-forward compensation term of the grid-side voltages is not considered, by using Mason’s signal-flow gain formula, the open-loop transfer function of the inner loop can be obtained as:

Fig. 6.Control model diagram of the inner current loop.

Where Gd(s)=1/(Td+1) is a first-order inertia plant that represents the delay caused by the sampling, program calculation and PWM control, and Td is the delay time.

For further analysis, (21) needs to be rearranged as:

Where a2 = Krp; a1 = 2ωc(Krp + Kr); a0 = Krp ;

b5 = Td LC；b4 = C(L + Td Rg + 2ωcTd L);

b3 = Td + RgC + Kv L + 2ωcTd RgC +2ωc LC + Td LC;

b2 = 1 + Kv Rg + 2ωc(Td + RgC + Kv L) +C(L + RgTd); and

b1 = 2ωc(Kv Rg + 1) + (Td + RgC + Kv L);

b0 = (Kv Rg + 1).

From (20), the gain of the quasi-PR controller at ω0 is Krp+Kr, which is still a large gain when compared to the PI controller at the same frequency. Hence, the accuracy in regulating the input ac signal can be guaranteed by adjusting the parameter Kr. In this paper, the gain of the GPR(s) at ω0 is set to 60 dB, namely:

Since Krp<

A stability analysis of the inner current loop using Routh-Hurwitz criterion involves very complicated mathematical calculations. For simplicity of analysis, the Frequency Response Method is used to select the proper controller parameter Krp. A Bode diagram of the open loop transfer function is presented in Fig. 7, where the parameters of the three-phase CSR system are configured as in Table I. As illustrated in Fig. 7, Krp has an important impact on the phase margin and bandwidth of the system. With an increase of Krp (from 0.1 to 3) at the beginning, the phase margin tends to increase. After that, it gradually drops. Finally, for Krp=3 the system becomes unstable (phase margin=-2.5°).

Fig. 7.Bode diagram of the inner-current open-loop with differing Krp

TABLE IPARAMETERS OF THE CSR SYSTEM

Generally, the bandwidth of the transfer function can be defined as the cutoff frequency where has an attenuated gain of 3 dB with respect to the dc gain [30]. In order to improve the dynamic performance of the inner current loop, Krp should be as large as possible to achieve a proper bandwidth as long as the system has enough of a stability margin. Based on the principle discussed above, Krp=0.2 is determined.

It is clear from Fig. 7 that the low-frequency gain of the inner current loop is very small. Therefore, it fails to achieve a fast dynamic response performance. In order to mitigate this problem, the control structure needs to be modified. In this paper, a new cascaded lead-lag compensator for the inner current loop is proposed as:

In the low-frequency region, if ω<ωa<ωb, the amplitude of (24) is equal to:

By selecting an appropriate parameter KL, let equation (25) be much more than 1 so that the proposed compensator is able to increase the low-frequency loop gain. Moreover, the bandwidth of the inner current controller should be chosen so that it is between 10 times the fundamental frequency and 1/10 the switching frequency to ensure both a fast response and switching noise rejection in practical applications. For simplicity of the design process, the single-input single-output (SISO) tool in MATLAB is used here to determine the parameters ωa and ωb while considering the stability margin and the low-frequency loop gain.

B. Inner Loop Design in the z-Domain

To further simplify the block diagram and to convert the model to a discrete-time, the digital implementation of the inner current loop is shown in Fig. 8. ZOH stands for a zero-order holder, and z-1 represents the sampling and PWM updating delay.

Fig. 8.Block diagram of the inner current loop in discrete-time domain.

The inner current loop is analyzed in the discrete-time domain, and it can be noted that the control plant includes two parts: the transform functions from the filter capacitor voltage to the ac-side current (Gv2i(s)), and the grid-side current to the filter capacitor voltage (Gg2v(s)) which can be expressed as:

By applying the ZOH transformation, the discrete-time domain transfer function of (26) is obtained as:

Where and

Since the grid-side current and capacitor voltage are sampled simultaneously, there is no additional delay in the control plant [31]. Therefore, by using an impulse invariant transformation, the discrete-time domain transfer function of (27) is derived as:

Obviously, RgTs/L<<1, and (29) can be approximated as:

In addition, for digital implementation, the PR controller is typically decomposed into two simple integrators, where the direct integrator is discretized with forward difference, and the feedback integrator is discretized with backward difference [32] [33]. Utilizing this method, the corresponding discrete-time domain transfer function of (20) is obtained as:

By using a bi-linear transformation and substituting (32) into (24), a discrete transfer function of the lead-lag compensator can be given by:

By the aforementioned process, and considering the active damping feedback loop, the open-loop and closed-loop transfer functions of the inner current loop in the discrete-time domain are established as:

Finally, using digital implementation of the open-loop transfer function in (34), the parameters of (24) are designed as KL=0.82, ωa=416.7 and ωb=5.3. A Bode plot of the open-loop transfer functions with/without the cascaded compensator is shown in Fig. 9. After compensation, the cross-over frequency is about 511 Hz with a phase margin of 57.2°, and the loop gain at the low frequency band is increased to 25 dB. As a result, the corresponding response speed and stability of the overall system are improved.

Fig. 9.Bode diagram of the inner-current open-loop.

Fig. 10 gives a bode plot of the inner-current closed-loop, which has a closed loop unity gain with zero phase angle in the low-frequency region. As a result, the closed-loop transfer function of the ac current controller Tci(z) can be simplified to a first-order inertia link 1/(1+Tcs) in the bandwidth region of the dc current control, where Tc represent the equivalent time constant.

Fig. 10.Bode diagram of the inner-current closed-loop.

C. Outer Current Controller Design

For the multi-loop control system, the outer controller gains are tuned with a limited bandwidth, which avoids the interference between the outer current control and the inner current control loops. Like the design procedure of the inner loop, the outer loop design can also use the MATLAB/SISO tools. A digital control block diagram model of the outer current loop is shown in Fig. 11, and the open-loop transfer function (Too(z)) is given by:

Fig. 11.Block diagram of the outer current loop in discrete-time domain.

When the outer current controller parameters are chosen as Kp=0.57 and Ki=4350, Bode plots of the open-loop and closed-loop systems with the compensation are depicted in Fig. 12. It is clear that the open-loop response is stable with a phase margin of 57.9º. Meanwhile, the closed-loop response meets the design requirements (Bandwidth=147 Hz).

Fig. 12.Bode diagram of the open- and closed-loop system with compensation.

Fig. 13 shows the step response of the proposed controller against the uncompensated controller. The two controllers have similar dynamic performances. However, the proposed controller exhibits a smaller steady-state error than that of the uncompensated controller.

Fig. 13.Step response of the proposed controller and the uncompensated controller.

D. Impact of the System Parameters

In particular, the parameters of the CSR system may vary due to changes in the ambient temperature and load. Therefore, it is necessary to consider system stability relating to changes in the parameters of the LC filter and load resistance. Figs. 14(a) and 14(b) show the migration of the poles and zeros of the closed-loop system when C and Lg change by ±50%, respectively. As shown in Fig. 14(a), the two dominant poles approach to the boundary of the unit circle as C increases, which may result in an unstable system. As shown in Fig. 14(b), all of the poles and zeros lie inside of the unit circle regardless of the increase of Lg. As a result, the system is far from instability.

Fig. 14.Polo-zero map of the digital control system corresponding to the change of the parameters of (a) C, (b) Lg and (C) RL.

When the load resistance (RL) changes by ±50%, Fig. 14(c) shows the migration of the poles and zeros of the closed-loop system. With an increase in RL, the domain poles tend toward the outside of the unit circle, which makes the overshoot of the system becomes higher (less damping of the dominant poles). When RL=0.65, the resulting overshoot is 12.2%, which is more than the expected 4%. If this is not allowable, Kp and Ki should be optimized.

 

V. SIMULATION RESULTS

To validate the performance of the proposed control scheme, the simulation of a three-phase CSR has been established using MATLAB/Simulink software. The circuit parameters for the simulation are listed in Table I.

Fig. 15 presents the steady state waveforms of the three-phase CSR system. The dc-link current reference value is set to 30A and the reactive power reference value q∗ is zero. From top to bottom, the curves in Fig. 15 are the grid-side current and dc-link current, the harmonic spectrum, the active power, the reactive power, and the power factor. It can be clearly seen that the instantaneous active power and instantaneous reactive power are kept constant, and that the dc-link current tracks its reference with good accuracy. The grid-side currents have nearly sinusoidal waveforms (THD=2.46%) and are in phase with the line voltages. Therefore, the unity power factor operation of the rectifier is successfully achieved.

Fig. 15.Simulation results in steady state for = 30A and q∗ = 0.

Fig. 16 shows the transient behavior of the grid-side current, the dc-link current, the instantaneous active and reactive power, and the power factor in the case of a sudden change from =0A to =60A. After a very short transient, the dc-link current tracks its reference with high rapidity and stability. In addition, the active power is kept constant, the reactive power is successfully reduced and kept close to zero, and the grid-side currents have nearly sinusoidal waveforms.

Fig. 16.Simulation results of transient change from = 0A to = 60A.

 

VI. EXPERIMENTAL VALIDATION

A prototype of the three-phase CSR, as shown in Fig. 17, has been built and tested in the laboratory. The control board is mainly composed of a digital signal processor (DSP) (TMS320F2808) and a preprocessing circuit. The IGBT modules used in the main circuit are PM400HSA120s, and the fast recovery diodes are RM300HA-24Fs. The grid-side voltage and filter capacitor voltage are sensed by a voltage Hall sensor (LV28-P). The grid-side current and dc-link current are separately measured by current Hall sensors (LA200-P and LT508-S). The parameters of the experimental system are the same as those used in the simulation model.

Fig. 17.Hardware prototype of the three-phase CSR system.

The Real Time Workshop (RTW) in Simulink is one of the DSP development tools, which has the capability to design a rapid prototyping system and to generate code directly from the Simulink models, and the entire running process is done automatically by using MATLAB/Simulink and Code Composer Studio (CCS V3.3) [34] [35]. In this study, the control strategy that was mentioned earlier in Section III is implemented using the TI C2000 package and TMS320F2808 toolbox, as shown in Fig. 18. The ADC block samples the grid-side voltage, the capacitance voltage, the grid-side current and the dc-link current sequentially. Then, these signals are scaled and transformed to obtain the actual variables in the α-β reference frame. The P-Q block is built based on equation (10), and it produces the grid-side reference current values. After that, the PR controllers generate the control signal by comparing the actual and the reference values of the grid-side current.

Fig. 18.Simulink model for control algorithms rapid implementation.

The experimental results with and without the active damping control are shown in Fig. 19. It can be seen that when Kv is initially zero, the grid-side current is highly distorted because of the input LC filter resonance. After the proposed method is enabled, the high frequency resonance is effectively suppressed and the THD value is reduced from 7.49% to 3.12%. Therefore, the performance of the CSR system meets the requirements of the grid code.

Fig. 19.Harmonic spectrum of grid-side current for (a) without the active damping method and (b) with the active damping method.

Fig. 20(a)-(d) shows the steady-state waveforms of the input voltage ea, grid-side current ia and dc-link current idc at different resistive loads. As can be seen, the grid-side current is nearly sinusoidal and in phase with the input voltage. This indicates that the proposed control strategy can provide a unity power factor and a low THD. It also indicates that the dc-link current can track its reference well with a small ripple.

Fig. 20.Experimental waveforms in steady state: (a) idc=20A, RL=0.5Ω; (b) idc=40A, RL=0.35Ω; (c) idc=40A, RL=0.5Ω; and (d) idc=40A, RL=0.6Ω.

To test the dynamic performance of the CSR system, the reference current command is changed from 0 to 60A. As shown in Fig. 21, the experimental results show that the dc-link current reaches a new stable state in approximately 32ms. They also show that the grid-side current tracks its reference phase within several switching cycles, exhibiting excellent dynamic performance.

Fig. 21.Experimental waveforms of transient response for the proposed strategy.

 

VII. CONCLUSIONS

In this paper, based on the instantaneous power theory, a novel control scheme for three-phase CSRs is proposed. The rotating transformation and phase detection of the input voltages are both eliminated. In order to suppress the LC resonances caused by the power source and the converter itself, the active damping method with capacitor voltage feedback is embedded into the control loop. However, a stability analysis is carried out to show that there is a limitation on the low frequency loop gain from the point of view of stability if a PR controller is used as the inner loop controller. Then, a dc steady-state error for the outer current loop is induced. A lead-lag cascaded compensator is proposed in this paper to solve this problem. Moreover, all of the controllers are designed based on the required phase margin and steady-state error using a bode diagram of the discrete-time domain of the system. Finally, the control algorithm is implemented using a DSP linked with MATLAB for automatic code generation. The results of the simulation and experiment demonstrate that the proposed strategy can achieve better steady state and transient performances.