DOI QR코드

DOI QR Code

An Analysis of Multi-processor System Performance Depending on the Input/Output Types

입출력 형태에 따른 다중처리기 시스템의 성능 분석

  • Received : 2016.11.21
  • Accepted : 2016.12.13
  • Published : 2016.12.30

Abstract

This study proposes a performance model of a shared bus multi-processor system and analyzes the effect of input/output types on system performance and overload of shared resources. This system performance model reflects the memory reference time in relation to the effect of input/output types on shared resources and the input/output processing time in relation to the input/output processor, disk buffer, and device standby places. In addition, it demonstrates the contribution of input/output types to system performance for comprehensive analysis of system performance. As the concept of workload in the probability theory and the presented model are utilized, the result of operating and analyzing the model in various conditions of processor capability, cache miss ratio, page fault ratio, disk buffer hit ratio (input/output processor and controller), memory access time, and input/output block size. A simulation is conducted to verify the analysis result.

Keywords

References

  1. Wen-Tsuen Chen and Jang-Ping Sheu, "Performance Analysis of Multiple Bus Interconnection Networks with Hierarchical Requesting Model," IEEE Trans. on Computer, vol. 50, No. 7, pp. 834-842.
  2. Men-Chow Chiang and Gurindar S. Sohi, "Experience with Mean Value Analysis Models for Evaluating Shared Bus, Throughput-Oriented Multiprocessors," Performance Evaluating Review, vol. 19, May 2003, pp. 90-102.
  3. J. L. Grino et al., "Analysis and Simulation of Multiplexed Single-Bus Networks with and without Buffering," Proc. of Symposium on Computer Architeture, 1995, pp. 414-421.
  4. Qing Yang and Laxmi N. Bhuyan, "Analysis of Packet-Switched Multiple-Bus Multiproessor Systems," IEEE Trans. on Computer, vol. 50, March 2001, pp.352-357.
  5. Janaki Akella and Daniel P. Siewiorek, "Modeling and Measurement of the Impact of Input and Output on System Performance," Proc. of Symposium on Computer Architecture, 2005, pp. 390-399.
  6. Men-Chow Chiang and Gurindar S. Sohi, "Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment," IEEE Trans. on Computer, vol. 51, No. 3, pp. 297-317.
  7. Per Stenstrom, "A Survey of Cache Coherence Schemes for Multiprocessors," IEEE Computer, June 2000, pp. 12-24.
  8. 장범환, "트래픽 세션의 포트 역할을 이용한 네트워크 공격 시각화," 디지털산업정보학회 논문지, 11권 4호, 2015, pp.47-60.
  9. 양환석, "Mobile Ad-hoc Network에서 영역 기반 보안 멀티캐스트 기법 연구," 디지털산업정보학회 논문지, 12권 3호, 2016, pp.75-85.