Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Hardware Design of High Performance Arithmetic Unit with Processing of Complex Data for Multimedia Processor

복소수 데이터 처리가 가능한 멀티미디어 프로세서용 고성능 연산회로의 하드웨어 설계

  • Received : 2015.11.23
  • Accepted : 2016.01.04
  • Published : 2016.01.31
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Abstract

In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.

본 논문에서는 멀티미디어용 알고리즘을 고속으로 처리하기 위한 고성능 연산 회로를 설계하였다. 3단 파이프라인 구조로 동작하는 연산회로는 4개의 16-비트${\times}$16-비트 곱셈기의 효율적인 구성, 캐리 보존 형식 데이터에 대한 새로운 부호 확장 기법과 다수 개의 부분 곱셈 결과의 통합과정에 부호 확장을 제거하는 교정 상수 기법을 사용하여 복소수 데이터와 가변 길이 고정 소수점 데이터에 대한 38개의 연산을 처리할 수 있다. 설계한 프로세서는 45nm CMOS 공정에서 최대 동작 속도는 300 MHz이며 약 37,000 게이트로 구성되며 300 MCOPS의 연산 성능을 갖는다. 연산 프로세서는 높은 연산 속도와 응용 분야에 특화된 다양한 연산 지원으로 멀티미디어 프로세서에 효율적으로 응용 가능하다.

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References

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