Journal of Power Electronics

The Korean Institute of Power Electronics (전력전자학회)
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Analysis and Design of a Separate Sampling Adaptive PID Algorithm for Digital DC-DC Converters

  • Chang, Changyuan (School of Integrated Circuits, Southeast University) ;
  • Zhao, Xin (School of Integrated Circuits, Southeast University) ;
  • Xu, Chunxue (School of Integrated Circuits, Southeast University) ;
  • Li, Yuanye (School of Integrated Circuits, Southeast University) ;
  • Wu, Cheng'en (School of Integrated Circuits, Southeast University)
  • Received : 2016.01.28
  • Accepted : 2016.06.14
  • Published : 2016.11.20
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Abstract

Based on the conventional PID algorithm and the adaptive PID (AD-PID) algorithm, a separate sampling adaptive PID (SSA-PID) algorithm is proposed to improve the transient response of digitally controlled DC-DC converters. The SSA-PID algorithm, which can be divided into an oversampled adaptive P (AD-P) control and an adaptive ID (AD-ID) control, adopts a higher sampling frequency for AD-P control and a conventional sampling frequency for AD-ID control. In addition, it can also adaptively adjust the PID parameters (i.e. $K_p$, $K_i$ and $K_d$) based on the system state. Simulation results show that the proposed algorithm has better line transient and load transient responses than the conventional PID and AD-PID algorithms. Compared with the conventional PID and AD-PID algorithms, the experimental results based on a FPGA indicate that the recovery time of the SSA-PID algorithm is reduced by 80% and 67% separately, and that overshoot is decreased by 33% and 12% for a 700mA load step. Moreover, the SSA-PID algorithm can achieve zero overshoot during startup.

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References

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